584 soc engineer jobs at 166 companies in Brisbane, CA
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Senior SOC Design Engineer
Santa Clara, California, United States
$136k-$265k/yr HybridFull Time
3+ YOEBS/MS in Computer or Electrical Engineering (or equivalent), 3+ years chip design experience focused on SoC integration and automation; expertise in RTL, SOC integration, design automation; scripting with Perl or Python; strong analytical and communication skills.
Perl, Python, RTL, EDA tools
3mo
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SoC Platform Engineer
Saratoga, California, United States
$150k-$220k/yr OnsiteFull Time
Experience with IP integration, system verification, firmware for SoC; RTL, AMBA interconnects; C/Python scripting; ARM architecture.
SystemVerilog, VHDL, UVM, C, Python, Tcl, Bash, Makefiles, Git, VCS, Questa, Xcelium, JTAG
1w
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Principal Engineer, SOC Integration
San Jose, California, United States
$219k-$351k/yr OnsiteFull Time
18+ YOEBS/MS in Computer/Electrical Engineering or CS with extensive ASIC/SoC experience (18+ years MS or 20+ years BS). Hands-on ASIC tape-out, commercial IPs (UCIe, CPU, DDR, Ethernet), SoC synthesis/timing/DFT, AMBA/ARM experience.
UCIe, ARM, DDR, Ethernet, AMBA, DFT, CDC
2mo
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SOC Intergration Engineer
Mountain View, California, United States
$120k-$600k/yr HybridFull Time
SystemVerilog; Python/Perl; experience integrating CPUs/GPUs/accelerators; SOC RTL; timing constraints; DV automation; emulation/verification familiarity.
SystemVerilog, Python, Perl, RTL design, DV tooling, Synthesis
2w
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SoC Verification Engineer
Austin or Santa Clara or Hillsboro
$142k-$200k/yr HybridFull Time
3+ YOE3+ years SoC design verification experience (4+ with bachelor's) with OVM/UVM, AMBA protocols, UVM testbench creation, debugging, and test planning; bachelor's or master's in EE/CE/CS or related.
OVM, UVM, CHI, AXI, AHB, APB, VIP, emulation models, system simulation tools
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SOC Integration Engineer
Mountain View, California, United States
$120k-$600k/yr HybridFull Time
Proficiency in SystemVerilog and scripting (Python/Perl), experience integrating SoC subsystems, defining timing/clock/reset methodologies, synthesis/linting/timing validation, and familiarity with high-speed interconnects (UCIE) and emulation; must be authorized to work in the US.
SystemVerilog, Python, Perl, UCIE
3w
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SoC QoS/Fabric Performance Engineer, Platform Architecture
Cupertino, California, United States
OnsiteFull Time
Experienced SoC performance engineer to work with hardware and software teams to shape SoC architecture and develop on-chip interconnect and memory QoS features.
1mo
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SoC Verification Engineer – NoC / UVM
San Jose, California, United States
$146k-$250k/yr HybridFull Time
Expertise in SystemVerilog and UVM, ASIC/SoC verification, constraint-random and coverage-driven methodologies, formal verification (SVA); experience with Synopsys VCS and Cadence IES preferred; B.S. or M.S. in computer/electrical engineering.
SystemVerilog, UVM, OVM, VMM, Verilog, SystemVerilog Assertions (SVA), Synopsys VCS, Cadence IES, Cadence IEV, Jasper, Synopsys VC-Formal, Magellan
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SoC DFT Engineer, Cloud
Sunnyvale, California, United States
$163k-$237k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE/CS or equivalent; 5+ years DFT architecture/implementation/verification for SoCs; silicon bring-up and test methodology experience (ATE, MBIST, JTAG, SLT); familiarity with fault models and EDA DFT tools; Master's/PhD and 10+ years preferred.
ATE, MBIST, JTAG, System Level Test (SLT), Synopsys, Design Compiler, DFT Max, Siemens EDA, Tessent, TestKompress, IEEE 1149.1, IEEE 1687, BSDL, STIL, ATPG, iJTAG, TAP
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SoC Design Engineer
Santa Clara, California, United States
$157k-$160k/yr OnsiteFull Time
1+ YOEMaster's in Electrical or Computer Engineering required, 1+ year digital design experience; RTL/Verilog, SystemVerilog/SVA, Python, Perl; experience with Synopsys PrimeTime, Cadence Virtuoso, Design Compiler, Integrator; FPGA prototyping, STA, DFT.
Synopsys PrimeTime, Cadence Virtuoso, Design Compiler, Integrator, SystemVerilog, SVA, Python, Perl, Verilog, FPGA
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Sr. Principal Engineer, SoC Architect
San Jose, California, United States
$250k-$304k/yr OnsiteFull Time
15+ YOE15+ years in SoC/system architecture; strong high-speed I/O and interconnect knowledge; leadership, cross-functional collaboration.
PCIe, PCIe Gen5, PCIe Gen6, CXL/UCIe, HBM, SerDes, Ethernet, USB, Memory interconnect, Interconnect
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Senior Engineer, SoC Architecture – Memory Subsystem and Interconnect
Mountain View, California, United States
$159k-$218k/yr OnsiteFull Time
7+ YOEBSc/Masters/PhD in CS/Engineering (or equivalent), >7 years experience in fabric/system cache/DRAM controller architecture, 3+ years in SoC/ASIC design, knowledge of memory controllers, ARM bus protocols, JEDEC memory standards.
BookSim Simulator, Platform Architect, ARM, ACE, AXI, AHB, JEDEC, LPDDR, DDR, HBM
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SoC Architect
San Jose, California, United States
$323k-$437k/yr HybridFull Time
10+ YOE10+ years in semiconductor SoC architecture, Bachelor's or Master's in Electrical/Computer Engineering, expertise in interconnect, power, caching, packaging, memory and performance/power modeling, strong communication and influencing skills.
2mo
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SoC Architect
San Jose or United States
$175k-$350k/yr HybridFull Time
18+ YOEBachelor's/Master's/PhD in EE/Computer Engineering or related; 18+ years in SoC/system architecture; expertise in high-speed IO, data movement, performance modeling, and cross-functional collaboration.
UCIe, PCIe, CXL, UALink, ESUN, Ethernet
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SoC Architect
Santa Clara, California, United States
$175k-$265k/yr HybridFull Time
d-Matrix: Develops high-performance semiconductor chips for generative AI inference.
5+ YOEMS in CS/ECE or related with 5+ years in SoC/compute architecture; expert in AI SoC architecture, performance modeling, ML (transformer/CNN/RNN), workload analysis; strong Python; C/C++ preferred; leadership in architecture delivery.
Python, C, C++
3mo
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Senior Staff SoC Design Engineer
Santa Clara, California, United States
$134k-$201k/yr OnsiteFull Time
5+ YOEBachelor's in CS/EE with 5-10 years; or Master's/PhD with 3-5 years; strong SystemVerilog RTL; SoC integration; AMBA AXI; scripting (Python/Tcl).
SystemVerilog, AMBA AXI, Python, Tcl, Synthesis, CDC/RDC, UCIe, UALink
3w
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Lead SoC Verification Engineer
Los Altos, California, United States
OnsiteFull Time
Anodize: Developing next-generation personal computing hardware and consumer electronics.
10+ YOE10+ years verifying complex ASICs; BS/MS in EE or CE; deep knowledge of AMBA interconnects; fluent in SystemVerilog/SystemC and UVM; UPF and multi-power-domain verification experience; proven silicon bring-up track record.
SystemVerilog, SystemC, UVM, AMBA CHI, AMBA AXI, AXI-S, APB, UPF
5d
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Sr. SOC Emulation Engineer, Silicon and Systems Group
Sunnyvale, California, United States
$183k-$248k/yr OnsiteFull Time
10+ YOE10+ years SOC emulation experience, bachelor's in CS/CE/EE, proficiency with emulation platforms, HDLs, C/C++, scripting (Python/Tcl/Perl), strong debugging and verification skills.
Synopsys Zebu, Cadence Palladium, Mentor Veloce, Verilog, SystemVerilog, VHDL, C++, C, Python, Tcl, Perl, AMBA AXI4, UVM
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SoC Verification Lead
Santa Clara, California, United States
$232k-$368k/yr OnsiteFull Time
15+ YOE15+ years of ASIC/SoC functional verification experience; Bachelor's/Master's in EE/CE or equivalent; proficiency in SystemVerilog, UVM, C/C++; experience leading verification to tape-out and managing verification plans, schedules, and risk.
SystemVerilog, UVM, C, C++, EDA
2w
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SOC Verification and Methodology Engineer - SCL
Santa Clara, California, United States
$153k-$230k/yr OnsiteFull Time
2+ YOEDevelop and implement SOC verification methodologies, create and execute test plans, debug issues; requires SystemVerilog/UVM experience and design verification background.
SystemVerilog, UVM, Perl, Python
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