1w
Save
Mark Applied
Hide
Principal Engineer, SOC Integration
San Jose, California, United States
$219k-$351k/yr OnsiteFull Time
18+ YOEBS/MS in Computer/Electrical Engineering or CS with extensive ASIC/SoC experience (18+ years MS or 20+ years BS). Hands-on ASIC tape-out, commercial IPs (UCIe, CPU, DDR, Ethernet), SoC synthesis/timing/DFT, AMBA/ARM experience.
UCIe, ARM, DDR, Ethernet, AMBA, DFT, CDC
2w
Save
Mark Applied
Hide
SoC Verification Engineer
Austin or Santa Clara or Hillsboro
$142k-$200k/yr HybridFull Time
3+ YOE3+ years SoC design verification experience (4+ with bachelor's) with OVM/UVM, AMBA protocols, UVM testbench creation, debugging, and test planning; bachelor's or master's in EE/CE/CS or related.
OVM, UVM, CHI, AXI, AHB, APB, VIP, emulation models, system simulation tools
3w
Save
Mark Applied
Hide
SoC QoS/Fabric Performance Engineer, Platform Architecture
Cupertino, California, United States
OnsiteFull Time
Experienced SoC performance engineer to work with hardware and software teams to shape SoC architecture and develop on-chip interconnect and memory QoS features.
1mo
Save
Mark Applied
Hide
SoC Verification Engineer – NoC / UVM
San Jose, California, United States
$146k-$250k/yr HybridFull Time
Expertise in SystemVerilog and UVM, ASIC/SoC verification, constraint-random and coverage-driven methodologies, formal verification (SVA); experience with Synopsys VCS and Cadence IES preferred; B.S. or M.S. in computer/electrical engineering.
SystemVerilog, UVM, OVM, VMM, Verilog, SystemVerilog Assertions (SVA), Synopsys VCS, Cadence IES, Cadence IEV, Jasper, Synopsys VC-Formal, Magellan
1mo
Save
Mark Applied
Hide
SoC DFT Engineer, Cloud
Sunnyvale, California, United States
$163k-$237k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE/CS or equivalent; 5+ years DFT architecture/implementation/verification for SoCs; silicon bring-up and test methodology experience (ATE, MBIST, JTAG, SLT); familiarity with fault models and EDA DFT tools; Master's/PhD and 10+ years preferred.
ATE, MBIST, JTAG, System Level Test (SLT), Synopsys, Design Compiler, DFT Max, Siemens EDA, Tessent, TestKompress, IEEE 1149.1, IEEE 1687, BSDL, STIL, ATPG, iJTAG, TAP
1mo
Save
Mark Applied
Hide
SoC Design Engineer
Santa Clara, California, United States
$157k-$160k/yr OnsiteFull Time
1+ YOEMaster's in Electrical or Computer Engineering required, 1+ year digital design experience; RTL/Verilog, SystemVerilog/SVA, Python, Perl; experience with Synopsys PrimeTime, Cadence Virtuoso, Design Compiler, Integrator; FPGA prototyping, STA, DFT.
Synopsys PrimeTime, Cadence Virtuoso, Design Compiler, Integrator, SystemVerilog, SVA, Python, Perl, Verilog, FPGA
2mo
Save
Mark Applied
Hide
Sr. Principal Engineer, SoC Architect
San Jose, California, United States
$250k-$304k/yr OnsiteFull Time
15+ YOE15+ years in SoC/system architecture; strong high-speed I/O and interconnect knowledge; leadership, cross-functional collaboration.
PCIe, PCIe Gen5, PCIe Gen6, CXL/UCIe, HBM, SerDes, Ethernet, USB, Memory interconnect, Interconnect
2mo
Save
Mark Applied
Hide
SoC Architect
San Jose or United States
$175k-$350k/yr HybridFull Time
18+ YOEBachelor's/Master's/PhD in EE/Computer Engineering or related; 18+ years in SoC/system architecture; expertise in high-speed IO, data movement, performance modeling, and cross-functional collaboration.
UCIe, PCIe, CXL, UALink, ESUN, Ethernet
1mo
Save
Mark Applied
Hide
SoC Architect
Santa Clara, California, United States
$175k-$265k/yr HybridFull Time
d-Matrix: Develops high-performance semiconductor chips for generative AI inference.
5+ YOEMS in CS/ECE or related with 5+ years in SoC/compute architecture; expert in AI SoC architecture, performance modeling, ML (transformer/CNN/RNN), workload analysis; strong Python; C/C++ preferred; leadership in architecture delivery.
Python, C, C++
3mo
Save
Mark Applied
Hide
Senior Staff SoC Design Engineer
Santa Clara, California, United States
$134k-$201k/yr OnsiteFull Time
5+ YOEBachelor's in CS/EE with 5-10 years; or Master's/PhD with 3-5 years; strong SystemVerilog RTL; SoC integration; AMBA AXI; scripting (Python/Tcl).
SystemVerilog, AMBA AXI, Python, Tcl, Synthesis, CDC/RDC, UCIe, UALink
4d
Save
Mark Applied
Hide
Sr. SOC Emulation Engineer, Silicon and Systems Group
Sunnyvale, California, United States
$183k-$248k/yr OnsiteFull Time
10+ YOE10+ years SOC emulation experience, bachelor's in CS/CE/EE, proficiency with emulation platforms, HDLs, C/C++, scripting (Python/Tcl/Perl), strong debugging and verification skills.
Synopsys Zebu, Cadence Palladium, Mentor Veloce, Verilog, SystemVerilog, VHDL, C++, C, Python, Tcl, Perl, AMBA AXI4, UVM
1mo
Save
Mark Applied
Hide
SoC Verification Lead
Santa Clara, California, United States
$232k-$368k/yr OnsiteFull Time
15+ YOE15+ years of ASIC/SoC functional verification experience; Bachelor's/Master's in EE/CE or equivalent; proficiency in SystemVerilog, UVM, C/C++; experience leading verification to tape-out and managing verification plans, schedules, and risk.
SystemVerilog, UVM, C, C++, EDA
1mo
Save
Mark Applied
Hide
Lead SoC Architect - India
Sunnyvale or India
OnsiteFull Time
10+ YOERequires Bachelor's or Master's in EE/CE/CS, 10+ years SoC/ASIC experience, expertise in SoC subsystems (CPU/GPU/NPU, NoC, memory, PCIe), C/C++/SystemC modeling, RTL knowledge, and on-site presence in Sunnyvale.
C, C++, SystemC, Linux
3d
Save
Mark Applied
Hide
Datacenter Compute SoC Architect
San Jose or San Diego or Portland or Austin
$211k-$356k/yr OnsiteFull Time
10+ YOE10+ years SoC/compute architecture experience, 3+ years in datacenter/server SoCs; Bachelor’s degree in EE/CE/CS; expertise in CPU/memory/Interconnect, PCIe/CXL, and performance modeling.
C++, SystemC, UCIe, PCIe, CXL, ARM AMBA CHI, AXI
3w
Save
Mark Applied
Hide
SoC Digital Verification Engineer, Multimedia Lab
San Jose, California, United States
$156k-$317k/yr OnsiteFull Time
1+ YOEBachelor's in a related field,1+ years ASIC/SoC verification experience,mastery of SystemVerilog and UVM,proficiency with simulation/debug tools and Python/Perl/Shell scripting.
SystemVerilog, UVM, VCS, Incisive, Questa, Verdi, Python, Perl, Shell, Palladium, ZeBu, JasperGold, FPGA, ASIC
2mo
Save
Mark Applied
Hide
Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Irvine or Austin or Sunnyvale
$160k-$220k/yr OnsiteFull Time
5+ YOEBachelor’s degree in electrical engineering, computer engineering or computer science; 5+ years ASIC/physical design experience; strong EDA tool knowledge; scripting skills; ability to work extended hours.
EDA tools, Python, Csh/Bash/Shell, Perl, TCL, Makefile
2mo
Save
Mark Applied
Hide
Sr. Principal SoC Architect (AI2501)
San Jose, California, United States
$231k-$358k/yr OnsiteFull Time
20+ YOEMS or PhD in EE/CS, 20+ years developing hardware-focused products, 3+ years architecting and tape-out of complex ML SoCs, strong ML/math foundation, HW/SW co-design and industry/publication experience.
2w
Save
Mark Applied
Hide
Senior Hardware Engineer - SoC Electrical Failure Analysis (Hybrid)
San Jose, California, United States
$165k-$241k/yr HybridFull Time
Experience in post-silicon validation, SoC failure analysis, power/signal integrity, high-speed interfaces, and driving failure analysis; strong debugging, measurement, and software skills.
Python, C++, Oscilloscopes, VNA, BERT, logic analyzers
2mo
Save
Mark Applied
Hide
SoC Architect, Memory Subsystem
San Jose or Austin
$151k-$252k/yr OnsiteFull Time
6+ YOE6+ years in computer engineering/memory subsystems; strong knowledge of memory hierarchies, interfaces (DDR/LPDDR/HBM), controllers, caches; experience with PPA optimization; collaboration with software/hardware teams.
DDR memory interfaces, LPDDR, HBM, Memory controllers, Cache subsystems, Cache coherence protocols, Bus protocols (CHI, ACE, AXI), Android ecosystem, Arm architecture, Analysis tools
6d
Save
Mark Applied
Hide
ASIC Engineer, Design
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
6+ YOEBachelor's degree or equivalent,6+ years hardware design experience for production silicon,expertise in microarchitecture,RTL and SoC integration,strong communication and collaboration skills.
RTL, Synthesis, Timing Closure, Formal Verification Methodology, SoC, EMR
Explore Jobs