514 soc engineer jobs at 141 companies in Pinole, CA
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Senior SOC Design Engineer
Santa Clara, California, United States
$136k-$265k/yr HybridFull Time
3+ YOEBS/MS in Computer or Electrical Engineering (or equivalent), 3+ years chip design experience focused on SoC integration and automation; expertise in RTL, SOC integration, design automation; scripting with Perl or Python; strong analytical and communication skills.
Perl, Python, RTL, EDA tools
3mo
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SoC Platform Engineer
Saratoga, California, United States
$150k-$220k/yr OnsiteFull Time
Experience with IP integration, system verification, firmware for SoC; RTL, AMBA interconnects; C/Python scripting; ARM architecture.
SystemVerilog, VHDL, UVM, C, Python, Tcl, Bash, Makefiles, Git, VCS, Questa, Xcelium, JTAG
2mo
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SOC Intergration Engineer
Mountain View, California, United States
$120k-$600k/yr HybridFull Time
SystemVerilog; Python/Perl; experience integrating CPUs/GPUs/accelerators; SOC RTL; timing constraints; DV automation; emulation/verification familiarity.
SystemVerilog, Python, Perl, RTL design, DV tooling, Synthesis
3w
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SoC Verification Engineer
Austin or Santa Clara or Hillsboro
$142k-$200k/yr HybridFull Time
3+ YOE3+ years SoC design verification experience (4+ with bachelor's) with OVM/UVM, AMBA protocols, UVM testbench creation, debugging, and test planning; bachelor's or master's in EE/CE/CS or related.
OVM, UVM, CHI, AXI, AHB, APB, VIP, emulation models, system simulation tools
5d
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Staff SoC RTL Engineer
Burlingame, California, United States
$175k-$230k/yr HybridFull Time
5+ YOERequires BS, MS, or Ph.D. in engineering, 5+ years of SoC/ASIC front-end design, SystemVerilog or Verilog, computer architecture, low-power design, subsystem integration, and VCS with Verilog/C co-simulation.
SystemVerilog, Verilog, VCS, Verilog/C Co-Simulation, FPGA, PCIe, UCIe, DDR, NoC
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SOC Integration Engineer
Mountain View, California, United States
$120k-$600k/yr HybridFull Time
Proficiency in SystemVerilog and scripting (Python/Perl), experience integrating SoC subsystems, defining timing/clock/reset methodologies, synthesis/linting/timing validation, and familiarity with high-speed interconnects (UCIE) and emulation; must be authorized to work in the US.
SystemVerilog, Python, Perl, UCIE
4w
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SoC QoS/Fabric Performance Engineer, Platform Architecture
Cupertino, California, United States
OnsiteFull Time
Experienced SoC performance engineer to work with hardware and software teams to shape SoC architecture and develop on-chip interconnect and memory QoS features.
1mo
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SoC DFT Engineer, Cloud
Sunnyvale, California, United States
$163k-$237k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE/CS or equivalent; 5+ years DFT architecture/implementation/verification for SoCs; silicon bring-up and test methodology experience (ATE, MBIST, JTAG, SLT); familiarity with fault models and EDA DFT tools; Master's/PhD and 10+ years preferred.
ATE, MBIST, JTAG, System Level Test (SLT), Synopsys, Design Compiler, DFT Max, Siemens EDA, Tessent, TestKompress, IEEE 1149.1, IEEE 1687, BSDL, STIL, ATPG, iJTAG, TAP
1d
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Senior SOC Physical Design Engineer
Santa Clara, California, United States
$147k-$190k/yr OnsiteFull Time
Master's degree in electrical, computer, or related engineering, computer science, or related field; expertise in SoC physical design, verification, timing closure, and tapeout signoff.
2mo
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SoC Design Engineer
Santa Clara, California, United States
$157k-$160k/yr OnsiteFull Time
1+ YOEMaster's in Electrical or Computer Engineering required, 1+ year digital design experience; RTL/Verilog, SystemVerilog/SVA, Python, Perl; experience with Synopsys PrimeTime, Cadence Virtuoso, Design Compiler, Integrator; FPGA prototyping, STA, DFT.
Synopsys PrimeTime, Cadence Virtuoso, Design Compiler, Integrator, SystemVerilog, SVA, Python, Perl, Verilog, FPGA
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Senior Engineer, SoC Architecture – Memory Subsystem and Interconnect
Mountain View, California, United States
$159k-$218k/yr OnsiteFull Time
7+ YOEBSc/Masters/PhD in CS/Engineering (or equivalent), >7 years experience in fabric/system cache/DRAM controller architecture, 3+ years in SoC/ASIC design, knowledge of memory controllers, ARM bus protocols, JEDEC memory standards.
BookSim Simulator, Platform Architect, ARM, ACE, AXI, AHB, JEDEC, LPDDR, DDR, HBM
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SoC Architect
Santa Clara, California, United States
$175k-$265k/yr HybridFull Time
d-Matrix: Develops high-performance semiconductor chips for generative AI inference.
5+ YOEMS in CS/ECE or related with 5+ years in SoC/compute architecture; expert in AI SoC architecture, performance modeling, ML (transformer/CNN/RNN), workload analysis; strong Python; C/C++ preferred; leadership in architecture delivery.
Python, C, C++
4w
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Lead SoC Verification Engineer
Los Altos, California, United States
OnsiteFull Time
Anodize: Developing next-generation personal computing hardware and consumer electronics.
10+ YOE10+ years verifying complex ASICs; BS/MS in EE or CE; deep knowledge of AMBA interconnects; fluent in SystemVerilog/SystemC and UVM; UPF and multi-power-domain verification experience; proven silicon bring-up track record.
SystemVerilog, SystemC, UVM, AMBA CHI, AMBA AXI, AXI-S, APB, UPF
1w
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Sr. SOC Emulation Engineer, Silicon and Systems Group
Sunnyvale, California, United States
$183k-$248k/yr OnsiteFull Time
10+ YOE10+ years SOC emulation experience, bachelor's in CS/CE/EE, proficiency with emulation platforms, HDLs, C/C++, scripting (Python/Tcl/Perl), strong debugging and verification skills.
Synopsys Zebu, Cadence Palladium, Mentor Veloce, Verilog, SystemVerilog, VHDL, C++, C, Python, Tcl, Perl, AMBA AXI4, UVM
2mo
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SoC Verification Lead
Santa Clara, California, United States
$232k-$368k/yr OnsiteFull Time
15+ YOE15+ years of ASIC/SoC functional verification experience; Bachelor's/Master's in EE/CE or equivalent; proficiency in SystemVerilog, UVM, C/C++; experience leading verification to tape-out and managing verification plans, schedules, and risk.
SystemVerilog, UVM, C, C++, EDA
1mo
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Principal SoC Architect
Walnut Creek, California, United States
$168k-$300k/yr OnsiteFull Time
12+ YOEBachelor's degree in electrical or computer engineering; 12+ years in ARM-based SoC architecture and silicon development; experience with memory, IO virtualization, Ethernet, PCIe, memory subsystems, and NoC.
ARM, Ethernet, PCIe, NoC, RTL, Tcl, Perl, Python
1w
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SoC Architect
Mountain View, California, United States
$251k-$310k/yr HybridFull Time
10+ YOEMS or equivalent,10+ years ASIC/SoC digital design and microarchitecture experience, ownership of major design blocks and successful tapeouts, SystemVerilog expertise, Python/C++ fluency, strong debug and leadership skills.
SystemVerilog, Python, C++, Chisel (Scala)
5d
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ASIC/SOC DFT Engineer (Silicon Engineering)
Austin or Palo Alto
OnsiteFull Time
1+ YOEBachelor's degree in electrical engineering, computer engineering, or computer science; 1+ year ASIC experience; scan insertion or DFT setup experience; scripting and Verilog/SystemVerilog skills preferred.
csh, bash, Perl, Python, Verilog, SystemVerilog, UPF, DRC
1mo
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Lead SoC Architect - India
Sunnyvale or India
OnsiteFull Time
10+ YOERequires Bachelor's or Master's in EE/CE/CS, 10+ years SoC/ASIC experience, expertise in SoC subsystems (CPU/GPU/NPU, NoC, memory, PCIe), C/C++/SystemC modeling, RTL knowledge, and on-site presence in Sunnyvale.
C, C++, SystemC, Linux
2mo
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AI SOC Architect
Los Altos, California, United States
OnsiteFull Time
10+ YOEBachelor's in EE/CE (Master's preferred), 10+ years SoC/compute architecture experience with RISC-V and AI acceleration, expertise in multicore clusters, memory hierarchies, performance modeling, and strong communication skills.
RISC-V, AXI, UALINK, HBM, RTL
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