67 soc engineer jobs at 39 companies in Rubidoux, CA
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Wireless SOC Verification Engineer
Irvine, California, United States
OnsiteFull Time
Experience verifying complex SoCs using UVM testbenches, developing coverage-driven and directed tests, deploying AI tools, and collaborating across product teams to improve tape-out readiness.
UVM
2mo
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Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Irvine or Austin or Sunnyvale
$160k-$220k/yr OnsiteFull Time
5+ YOEBachelor’s degree in electrical engineering, computer engineering or computer science; 5+ years ASIC/physical design experience; strong EDA tool knowledge; scripting skills; ability to work extended hours.
EDA tools, Python, Csh/Bash/Shell, Perl, TCL, Makefile
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Senior Principal Digital Engineer
Los Angeles, California, United States
$156k-$235k/yr OnsiteFull Time
8+ YOEU.S. citizen with active Secret clearance. Requires extensive high-speed digital design and verification experience, FPGA/SoC/ASIC implementation skills (VHDL/Verilog), and STEM degree with significant experience.
VHDL, Verilog, System Verilog, UVM, MATLAB, Simulink, FPGA, SoC, ASIC, Electronic Hardware-In-Loop
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Payload Software Engineer
Irvine, California, United States
$155k-$175k/yr OnsiteFull Time
6+ YOE6+ years in embedded software using C, C++, and Python; experience with SoC/microcontroller design, Embedded Linux/Yocto, ICD development, communication protocols, and full software lifecycle from requirements to test.
C, C++, Python, Embedded Linux, Yocto, FPGA, SoC, Microcontroller
3mo
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Senior Avionics FPGA Design & Verification Engineer - TeraWave
Seattle or Los Angeles or Denver
$157k-$220k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
7+ YOE7+ years in digital design/SoC architecture; SystemVerilog/Verilog RTL; FPGA/SoC integration; timing and bus protocols; RTL simulation and debugging; hardware design verification.
SystemVerilog, Verilog, QuestaSim, FPGA, SoC, RTL, AXI, AHB
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Senior Security Engineer
Boston or Chicago or Los Angeles or New York or San Francisco or Toronto or Vancouver or Vancouver
$145k-$175k/yr RemoteFull Time
5+ YOE5+ years security engineering experience; strong application, cloud, and infrastructure security; SOC 2 and compliance experience; vulnerability management, IaC and CI/CD security; strong communication and software engineering skills.
OWASP, NIST, CIS Controls, SOC 2, ISO 27001, AWS Security Hub, Azure Security Center, GCP Security Command Center, SIEM, SOAR, Terraform, CloudFormation, C#, CI/CD
1w
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Hardware Engineer
Colorado Springs or Irvine or Longmont or Fremont or Rochester or San Jose
$91k-$113k/yr OnsiteFull Time
Early-career candidates pursuing or recently completing an engineering degree; familiarity with hardware, firmware, ASIC/SoC, or systems; programming and design experience through coursework or projects; strong analytical and communication skills.
Verilog/SystemVerilog, RTL, FPGA, C, C++, Assembly, Python, Java, Go, SQL, JavaScript, Git, Linux, IDE, CAD, Microsoft Office, RTOS
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Sr. FPGA Engineer
El Segundo or Los Angeles or Hawthorne
$160k-$225k/yr OnsiteFull Time
5+ YOEB.S. in engineering or CS, 5+ years FPGA/RTL experience, Verilog/SystemVerilog, Vivado toolchain, AXI protocols, ARM/SoC FPGA experience, Python/Bash scripting, U.S. Person status required.
Verilog, SystemVerilog, ARM AMBA AXI Protocol (AXI4, AXI4-Lite, AXI4-Stream), Vivado Design Suite, Zynq, Ultrascale, Ultrascale+, Versal, TCP/UDP/IP, I2C, JTAG, UART, SPI, CAN, Bash, Python, Simulink, MATLAB, C, C++, SystemC, Chisel, VHDL, git, Bitbucket CI, Jenkins, NTP, PTP, Ettus, NI, HackRF, HLS Synthesis, GPU
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Lead Hardware Engineer
Long Beach, California, United States
$151k-$227k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE, 5+ years electronics design for harsh environments, experience leading engineers, driving engineering processes, and delivering avionics hardware across full product lifecycle.
SPI, PCIe, Ethernet, ADC, DAC, DC-DC converters, SoC, microcontroller, microprocessor
3w
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Sr. Systems Engineer
Los Angeles, California, United States
$88k-$131k/yr HybridFull Time
5+ YOE5+ years systems engineering experience; expertise with Kubernetes, Linux, cloud operations (Azure preferred); automation with Git Ops, Ansible, Terraform, Claude AI; monitoring with Datadog/Prometheus; scripting in Python/Bash/PowerShell; security/compliance (PCI DSS, SOC 2); on-call participation.
Kubernetes, Linux, Azure, Git Ops, Ansible, Terraform, Claude AI, Datadog, Prometheus, Python, Bash, PowerShell
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Security Engineer
San Francisco or Palo Alto or Toronto or Los Angeles
OnsiteFull Time
Hands-on Python and AWS experience, cloud and application security, vulnerability management, IAM and secrets management, familiarity with SOC 2/ISO 27001, strong communication and threat modeling skills.
Python, AWS, Drata, Infisical, Bugcrowd, SOC 2, ISO 27001
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IP Release Principal Engineer
Santa Clara or Irvine
$159k-$238k/yr OnsiteFull Time
5+ YOEBachelor's or advanced degree (or equivalent experience) with 5+ years' SoC/IP delivery experience; expertise in RTL static checks, synthesis (SDC/UPF), DFT, Verilog, Perl/Python, and SoC integration; strong communication skills.
Lint, CDC, RDC, UPF, SDC, Perl, Python, Verilog, Jira, IPMP, JTAG, BIST, PCIE/CXL
2w
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Senior RF Digital Payload Engineer II Pipeline
Long Beach, California, United States
$145k-$210k/yr OnsiteFull Time
8+ YOEBachelor's in engineering or CS,8+ years space electronics experience,expertise in high-speed serial interfaces,SoC/microcontroller/DSP experience,US citizenship required.
SPI, PCIe, Ethernet
3w
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Digital Design Principal Engineer/Manager
Irvine, California, United States
$190k-$225k/yr OnsiteFull Time
20+ YOE20+ years FPGA/SoC development with leadership experience; MS in Electrical Engineering; deep Verilog/SystemVerilog expertise; FPGA/ASIC implementation and packet processing experience; scripting in C/C++, Perl, Tcl, Python.
Verilog, SystemVerilog, AMD (Xilinx Vivado), C, C++, Perl, Tcl, Python, Claude Code, Copilot
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FPGA Design Engineer
Irvine, California, United States
$100k-$140k/yr OnsiteFull Time
2+ YOEBS in EE or CS with 2+ years FPGA design; Xilinx FPGAs, SoCs, Vivado; TCL or Python; U.S. Person; background check and drug test.
Xilinx FPGAs, Vivado IDE, Tcl, Python, MATLAB, FPGA Design
1w
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Senior Electrical Engineer, Avionics
Los Angeles, California, United States
$160k-$200k/yr HybridFull Time
6+ YOE6+ years electrical engineering experience with PCB design, circuit simulation, wire harnessing, signal integrity, and prototype debugging; experience with Altium and LTSpice; strong DC power and high-speed interface knowledge.
Altium, LTSpice, HyperLynx, SIwave, Oscilloscope, Logic analyzer, Multimeter, Spectrum analyzer, FPGA, SoC
1d
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Principal Engineer-Communication Systems
Irvine or San Diego
$75k-$232k/yr OnsiteFull Time
8+ YOEMaster's or PhD in Electrical Engineering, 8+ years in wireless PHY systems design, signal processing and communication theory, and experience with MATLAB, C/C++, fixed-point simulation, modem design, and IC testing.
MATLAB, C, C++, Wi-Fi, Bluetooth, SoC
3mo
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Senior Staff Product Engineer
Irvine, California, United States
$141k-$172k/yr OnsiteFull Time
2+ YOEExperience delivering SOC products, knowledge of CMOS process and packaging, ATE experience, data-analysis tool proficiency, BS/MS/PhD in EE or related with relevant years, strong cross-functional and quality focus.
ATE, Verigy, Teradyne, Excel VBA, JMP, Galaxy, Data Conductor, PDF Exensio, Optimalplus
1mo
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Staff FPGA Engineer, EW
Costa Mesa, California, United States
$220k-$292k/yr OnsiteFull Time
Design and verify FPGA/DSP modules on AMD/Xilinx SoC/FPGA platforms; experience with HDL (VHDL/Verilog), high-speed digital interfaces (PCIe, JESD, Aurora), Linux development, Git and CI/CD; eligible for U.S. Secret clearance; mentoring experience.
AMD, Xilinx, VHDL, Verilog, Linux, Git, TCL, CI/HITL, PCIE, JESD, Aurora, AMD AIE
1w
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Senior ASIC Emulation Engineer
Los Angeles or United States
$170k-$250k/yr OnsiteFull Time
5+ YOE5+ years ASIC/SoC emulation experience, SystemVerilog and RTL knowledge, hands-on with Palladium/ZeBu/Veloce, scripting (Python/Perl/TCL), C/C++ firmware experience, and cross-functional debug skills.
Palladium, ZeBu, Veloce, SystemVerilog, Python, Perl, TCL, C, C++, APB, AHB, AXI, JTAG, SPI, HAPS, Protium, PCIe, Ethernet, USB, SERDES
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