3mo
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SoC Test Engineer
Austin or Cupertino or San Diego
OnsiteFull Time
10+ YOEBachelor's degree and 10+ years in SoC test engineering with strong programming and hardware test skills.
Teradyne UFlex, ip750, J750, Advantest 93k, Oscilloscope, Logic analyzer, PERL, C/C++, Visual Basic
2mo
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SoC Design Engineer
Austin, Texas, United States
$122k-$232k/yr HybridFull Time
3+ YOEBachelor's in Electrical/Computer Engineering; 3+ years in microarchitecture/RTL design; clock domain crossing, low-power design; RTL tools, SoC integration.
RTL design, SoC integration tools, NoC architectures, Low-power design, Power-area-timing optimization
1mo
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SOC Engineer
New Jersey or New York or Washington or Hawaii or Alaska or Maryland or Connecticut or Rhode Island or Massachusetts or Nevada or Oregon or Arizona or Colorado or Wyoming or Texas or North Dakota or Minnesota or Missouri or Illinois or Wisconsin or Florida or Georgia or Michigan or Ohio or Virginia or Pennsylvania or Delaware or Vermont or New Hampshire or Maine or Utah or Idaho or Montana or New Mexico or South Dakota or Nebraska or Kansas or Oklahoma or Iowa or Arkansas or Louisiana or Mississippi or Alabama or Tennessee or Kentucky or Indiana or South Carolina or North Carolina or West Virginia or California or United States
$84k-$162k/yr RemoteFull Time
2+ YOEIdentify, investigate, escalate, and remediate security alerts in a 24x7 SOC; manage and configure SOC tools; perform scripting/automation; 2+ years SOC experience; BS in CS/IT or equivalent; security certifications preferred.
ExtraHop, Qradar, Splunk, ServiceNow, SIEM Solutions, TrustWave, Microsoft 365 Security Suite, Endpoint Detection & Response Solutions, Email Protection Solutions, Web Content Filtering (WSS), Secure Web Gateway Solutions
1mo
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Principal SoC Design Engineer
Richardson, Texas, United States
$153k-$265k/yr OnsiteFull Time
8+ YOEBachelor's degree in EE/CE, 8+ years SoC/IP design experience, expert SystemVerilog/Verilog, knowledge of SoC interconnects (AXI, AHB, APB, CHI, NoC), scripting (Python/Tcl/Perl), experience with advanced nodes and silicon bring-up.
SystemVerilog, Verilog, Python, Tcl, Perl, AXI4, AXI5, AHB, APB, CHI, NoC, RISC-V, ARM Cortex, Synopsys DC, Genus, Verdi, IP-XACT, SystemRDL, UVM
1mo
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Principal SoC Design Engineer
Richardson, Texas, United States
$153k-$265k/yr OnsiteFull Time
8+ YOE8-10+ years in SoC/IP design for high-volume or safety-critical apps; strong SystemVerilog/Verilog; SoC interconnects (AXI4/5, AHB, CHI); RTL development on advanced nodes; scripting (Python, Tcl, Perl).
SystemVerilog, Verilog, AXI4/5, AHB, APB, CHI, NoC, RISC-V, ARM Cortex, Python, Tcl, Perl, Synopsys DC, Genus, Verdi
3w
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SOC IP Methodology Engineer - Custom SOC
Santa Clara or Austin or Hillsboro
$168k-$311k/yr OnsiteFull Time
8+ YOEMasters (8+ yrs) or BS (10+ yrs) with deep RTL-to-GDS methodology and physical design expertise, experience with EDA tool flows, IP ecosystems, customer-facing SOC development, DFT/BIST, synthesis/CTS/power/PNR, and scripting (Python/Perl/Tcl).
RTL-to-GDSII, Cadence, Synopsys, Mentor, Genus, First Encounter, Innovus, Design Compiler, Fusion Compiler, ICC2, PT-SI, Tempus, Redhawk, IP-XACT, Python, Perl, Tcl
2mo
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SOC Silicon Design Engineer
Austin or Boxborough
HybridFull Time
Design and develop custom silicon for CG SoC; collaborate across teams; strong analytical and communication skills.
Scripting (Perl, TCL, Python), EDA tools, VLSI design flow, CMOS technology
2mo
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Senior SOC Physical Design Engineer, HBM
Richardson, Texas, United States
OnsiteFull Time
3+ YOESenior SOC physical design engineer with hands-on experience in EDA tools, timing, power intent, DFT/MBIST, and HBM-based SoC integration.
Innovus, Fusion Compiler, IC Validator, Calibre, PrimeTime, Tempus, Synopsys Design Constraints, UPF, CPF, Ansys, Tcl, Python
1mo
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Staff SoC DFT Engineer, HBM
Richardson, Texas, United States
OnsiteFull Time
7+ YOE7+ years SoC DFT experience with scan/MBIST/LBIST, ATPG/JTAG, RTL-to-GDS flows, proficiency with EDA tools (Siemens, Synopsys, Cadence). Bachelor's in EE/CE or equivalent experience; scripting (Python, Tcl, Perl) preferred.
Siemens, Synopsys, Cadence, Python, Tcl, Perl, ATPG, JTAG, MBIST, LBIST
3w
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Senior SoC Performance Verification Engineer
Raleigh or Redmond or Austin
$120k-$235k/yr HybridFull Time
1+ YOEDoctorate/MS/BS in EE/CE/CS (or equivalent) with 1/4/5+ years technical engineering experience respectively; ability to pass Microsoft Cloud Background Check and export-control screening; SoC performance verification and System Verilog/UVM, C/C++ experience preferred.
System Verilog, UVM, C, C++
3w
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Staff SOC Physical Design Engineer
Austin, Texas, United States
$161k-$210k/yr OnsiteFull Time
3+ YOEExperience in SoC physical design flow (floorplanning, CTS, place-and-route, PDN, timing closure, LVS/DRC) with a Master's +3 years or Bachelor's +7 years in EE/CE/CS or related; strong cross-functional communication.
1d
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Staff Mixed-Signal SOC Engineer – Infrastructure Power
Austin, Texas, United States
HybridFull Time
7+ YOEMSEE or equivalent, 7+ years mixed-signal SoC experience with tapeout-to-production history; deep expertise in analog, digital, verification or system architecture; automated test and silicon validation experience; mentoring ability.
1w
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Custom SOC IP Verification Engineer
Santa Clara or Austin
$168k-$311k/yr OnsiteFull Time
6+ YOEB.S./M.S. in engineering or equivalent experience,6+ years ASIC verification with fabric/interconnect focus,proficient in SystemVerilog and UVM,experience with interconnect protocols and scripting (Python,Perl,TCL).
SystemVerilog, UVM, AMBA AXI, CHI, Python, Perl, TCL, Palladium, Veloce, SystemVerilog Assertions (SVA)
1mo
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SOC Analyst
Plano, Texas, United States
OnsiteFull Time
4+ YOEUS citizenship required; 4+ years SOC triage/response/detection engineering experience; expertise with EDR/ITDR/SIEM and cloud platforms (AWS/GCP/Azure); strong analytical, communication, and crisis-management skills; work onsite 10:30–18:30 CT with one weekend/month.
EDR, ITDR, SIEM, CrowdStrike Falcon, Falcon Fusion, Foundry, Immersive Labs, AWS, GCP, Azure, Linux, Windows
1mo
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Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Irvine or Austin or Sunnyvale
$160k-$220k/yr OnsiteFull Time
5+ YOEBachelor’s degree in electrical engineering, computer engineering or computer science; 5+ years ASIC/physical design experience; strong EDA tool knowledge; scripting skills; ability to work extended hours.
EDA tools, Python, Csh/Bash/Shell, Perl, TCL, Makefile
1mo
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SOC Analyst (782789)
Plano, Texas, United States
OnsiteFull Time
4+ YOEUS citizen required. 4+ years SOC experience in triage, response and detection engineering. Proficient with EDR/ITDR/SIEM, cloud (AWS/GCP/Azure), CrowdStrike Falcon, detection engineering, strong integrity; office-based with one weekend/month.
EDR, ITDR, SIEM, CrowdStrike Falcon, Falcon Fusion, Foundry, Immersive Labs, exposure management, AWS, GCP, Azure, Linux, Windows
2mo
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SoC Architect, Memory Subsystem
San Jose or Austin
$151k-$252k/yr OnsiteFull Time
6+ YOE6+ years in computer engineering/memory subsystems; strong knowledge of memory hierarchies, interfaces (DDR/LPDDR/HBM), controllers, caches; experience with PPA optimization; collaboration with software/hardware teams.
DDR memory interfaces, LPDDR, HBM, Memory controllers, Cache subsystems, Cache coherence protocols, Bus protocols (CHI, ACE, AXI), Android ecosystem, Arm architecture, Analysis tools
2mo
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Information Security Engineer - Security Operations (SOC)
Harris County, Texas, United States
OnsiteFull Time
2+ YOEBachelor's in Cybersecurity/IT or equivalent experience; 2+ years in SOC/SIEM engineering or detection/response; experience with Microsoft Sentinel, Microsoft Defender, Azure Logic Apps; KQL, MITRE ATT&CK, PowerShell/Python; security certifications preferred.
Microsoft Sentinel, Microsoft Defender, Azure Logic Apps, Rapid7, KQL, PowerShell, Python, MITRE ATT&CK
1mo
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Principal System Architect RF SoC - TeraWave
Seattle or San Francisco or Austin or Kent
$231k-$323k/yr HybridFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
10+ YOE10+ years RF systems design; Bachelor in Electrical or Computer Engineering; experience with MAC/PHY, DSP; Matlab, System C, C/C++; knowledge of OFDM, QAM, PCM/FM, PAM.
Matlab, SystemC, C/C++
1mo
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Staff Digital Design Engineer – SOC Low Power, Clocking & Integration
Austin, Texas, United States
$143k-$266k/yr HybridFull Time
10+ YOEBS/MS in Electrical Engineering, 10+ years digital CMOS IC design experience, expertise in Verilog/System Verilog, UPF/CPF, AXI/AHB/APB, RTL design, synthesis, timing, power analysis, simulation, scripting (Python/Perl/Tcl), and leading small teams.
Verilog, System Verilog, UPF, CPF, AXI, AHB, APB, RISC-V, C, Python, Perl, Tcl, Perforce, Git, Methodics
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