101 sta jobs at 34 companies in Daly City, CA
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STA Engineer
Santa Clara, California, United States
$153k-$230k/yr OnsiteFull Time
6+ YOE6+ years ASIC/SoC STA and synthesis experience with timing-closure, MMMC, low-power checks, SDC development, scripting (TCL/Perl), and hands-on use of PrimeTime and synthesis tools.
TCL, Perl, Python, Synopsys Prime Time, Synopsys Design Compiler, Cadence Genus, Conformal ECO Tool, PrimePower (PTPX)
3mo
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Senior Static Timing Analysis (STA) Methodology Engineer
Saratoga, California, United States
$120k-$220k/yr OnsiteFull Time
8+ YOESenior STA/Timing methodology engineer with 8+ years in STA, scripting (Tcl/Python/Perl), signoff; BS/MS in ECE or related; onsite in Saratoga, CA.
PrimeTime, PT-SI, PT-PX, PT-ECO, Tcl, Python, Perl
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ASIC DFT STA Technical Lead
San Jose or Santa Clara
$169k-$241k/yr OnsiteFull Time
3+ YOEDegree with relevant years of experience (Bachelors+8/Masters+6/PhD+3). Experience with RTL design, CDC/RDC, conformal verification, SDC development, timing constraint development, and scripting (Perl, TCL, Python, Makefile).
Perl, TCL, Python, Makefile, Synopsys PrimeTime, Synopsys Fusion, Design Compiler, Tessent
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STA/Constraints Engineer
Santa Clara, California, United States
HybridFull Time
Experience in STA, timing signoff, and physical design; expert use of PD tools (SNPS PT/GCA, ICC2/FC); scripting with Perl/TCL/Shell/Python; Verilog RTL experience; strong communication; Bachelor/Master preferred.
SNPS PT, GCA, ICC2, FC, Perl, TCL, Shell, Python, Verilog, SDC
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ASIC Implementation Engineer STA
San Jose, California, United States
$144k-$230k/yr OnsiteFull Time
12+ YOEBachelor's in EE or Computer Engineering, 12+ years ASIC STA experience, proficiency with Cadence or Synopsys sign-off flows, SDC/constraint development, and scripting in Tcl, Python, or Perl.
Tcl, Python, Perl, Shell, Cadence, Synopsys
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Physical Design Implementation and STA Lead
San Jose, California, United States
$149k-$215k/yr OnsiteFull Time
7+ YOEBachelor's in EE/CE,7+ years physical design/implementation experience,3+ years STA with Synopsys PrimeTime,block-level implementation skills,Proficiency in Tcl and Python,mentoring and leadership experience.
Synopsys PrimeTime, Tcl, Python
3w
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Static Timing Analysis Engineer, Full Chip STA
Mountain View, California, United States
$163k-$236k/yr OnsiteFull Time
8+ YOEBachelor's in EE/CS or equivalent,8+ years in silicon timing closure and chip integration, experience with PrimeTime/Tempus, STA signoff and constraint authoring, scripting with Tcl or Perl.
PrimeTime, Tempus, Tcl, Perl
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Sr. Staff Physical Design Timing Engineer (STA)
Boston or Mountain View or Toronto
$217k-$267k/yr HybridFull Time
12+ YOEBachelor's in EE/CE, 12 years physical design experience (minimum 5 years hands-on ASIC STA/timing closure), experience with Cadence or Synopsys flows, Tempus/PrimeTime, scripting (TCL, Python, PERL, Shell), strong problem-solving and communication.
Tempus, PrimeTime, Cadence, Synopsys, TCL, Python, PERL, Shell
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Principal Physical Design Engineer, STA
San Jose, California, United States
$209k-$250k/yr OnsiteFull Time
10+ YOE10+ years in timing analysis and sign-off for complex SoCs; Cadence/Synopsys flows; 7nm or below; scripting (Tcl/Python/Perl); able to work independently.
Cadence, Synopsys, Tcl, Python, Perl, SystemVerilog
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Senior ASIC Timing Engineer
Santa Clara or Durham or Austin or Hillsboro
$136k-$265k/yr HybridFull Time
3+ YOEBS in ECE + 5 years or MS + 3 years in timing/STA; hands-on full-chip and sub-chip STA, timing convergence, ECO implementation, physical design optimization, and deep sub-micron modeling.
STA, RTL, DFT, DFX, Formal Verification (FV)
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Senior DFT Engineer
Santa Clara, California, United States
$136k-$265k/yr HybridFull Time
3+ YOEExperience in scan test, BIST, ATPG, fault simulation; strong scripting (Perl/Python/Tcl); cross-functional RTL, STA, PnR exposure; silicon bring-up and ATE experience.
Perl, Python, Tcl, ATPG, STA, ATE
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Physcial Design Engineer
Mountain View, California, United States
$100k-$180k/yr OnsiteFull Time
8+ YOERequires 8–10 years of physical design and PnR experience, advanced-node expertise, and proficiency with floorplanning, CTS, routing, timing closure, STA, SDC, EMIR, PPA optimization, and EDA tools.
Synopsys Fusion Compiler, Synopsys ICC2, PrimeTime, Cadence Innovus, RedHawk, Voltus, GDSII, SDC, STA, EMIR
2mo
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Sr. Physical Design Engineer - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine Learning
Cupertino, California, United States
$183k-$248k/yr OnsiteFull Time
3+ YOESenior physical design STA engineer with strong timing analysis, scripting, and ASIC flow experience.
PrimeTime, Tempus, EEDA tools, Perl, Python, Javascript, SPICE, SPECTRE, DFT/DFX tools
3mo
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Physical Design Engineer, PnR
Austin or Fort Collins or Santa Clara
$100k-$500k/yr HybridFull Time
Synthesize, PNR, and STA for AI SoC partitions; use Synopsys tools; collaborate in a small PD team; knowledge of UPF/power domains and IP integration is a plus.
Synopsys Design Compiler, Fusion Compiler, IC Compiler II, Power domain tools, LEC/Formality, DRC/LVS, EM/IR, UPF, DFT (OCC/MBIST)
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Drivers — All Vehicle Classes
Seattle or San Francisco or Oakland or San Jose or Los Angeles or San Diego or Phoenix or Philadelphia or Dulles or Raleigh or Chicago or Houston or Dallas or Boston or New York City or Newark
FieldContract
Independent contractor driver with a valid driver's license, Class A CDL, TSA STA and TWIC credentials, commercial auto insurance, professional driving experience, and U.S. work authorization.
TSA Form 419F
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Warehouse Screener
South San Francisco, California, United States
$21-$23/hr OnsiteFull Time
2+ YOE2+ years air cargo and forklift experience; high school diploma or equivalent; ability to complete TSA training and STA background check; U.S. citizen or permanent resident required.
ETD, Metal Detectors, X-Ray, RF scanner, EMIS, K-9, Forklift
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Sr. / Staff ASIC Digital Design Engineer
San Jose, California, United States
OnsiteFull Time
6+ YOEExpertise in DFT, synthesis, power and timing analysis; tapeout experience; scripting (tcl/perl/python/shell); UPF and STA; Bachelors+8 years or Masters+6 years in engineering.
Synopsys, Siemens Tessent, PT, DC, VCLP, Formality, LEC, PrimeClosure, PrimePower, VCS, VC-spyglass-dft, Tetramax, Tessent, UPF, UNIX, Linux, tcl, perl, python, shell
3w
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ASIC Engineer, Implementation - Timing
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
6+ YOEBachelor's degree or equivalent,6+ years timing analysis experience, STA and timing-constraint development, knowledge of front-end and back-end ASIC flows, and cross-team communication skills.
PrimeTime, DMSA, Fusion Compiler, Innovus, Design Compiler, Genus
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Safety Manager II
San Francisco, California, United States
$120k-$158k/yr OnsiteFull Time
5+ YOEBachelor's in related field required, 5+ years construction/industrial safety experience, first aid/CPR and CHST preferred, experience with STA/JHA, audits, investigations, and mentoring safety teams.
1mo
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Physical Design Engineer II (eInfochips Inc)
San Jose, California, United States
OnsiteFull Time
7+ YOEBachelor's or equivalent, 7+ years physical design experience (synthesis, PnR, STA, timing convergence), proficiency with Innovus/Tempus/Quantus and TCL scripting, sub-7nm and SoC experience preferred.
Innovus, Tempus, Quantus, TCL, Cadence, Synopsys
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