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25 sta engineer jobs at 14 companies in Cedar Park, TX

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Senior STA Engineer
Austin, Texas, United States
$152k-$217k/yr OnsiteFull Time
MediaTek
MediaTekTaiwan Stock Exchange: 2454: Designs and develops system-on-chip solutions for electronic devices.
5+ YOE5+ years STA on high-performance CPU designs, expert multi-scenario STA/SDC, OCV/AOCV/POCV margining, Tempus/PrimeTime proficiency, scripting in Tcl/Python/Perl, advanced-node tape-out experience.
Cadence Tempus, Synopsys PrimeTime, Tcl, Python, Perl, ETM, Hyperscale
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GPU Physical Design Engineer, STA/Timing
Austin, Texas, United States
OnsiteFull Time
Apple
AppleNASDAQ: AAPL: Designs and sells consumer electronics, software, and online services.
Responsible for timing closure of complex GPU designs; collaborate with architecture, RTL, synthesis, clocking, DFT, physical and post-silicon teams to ensure timing convergence.
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2mo
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CPU Circuit Design Engineer
Austin, Texas, United States
$142k-$269k/yr HybridFull Time
Intel
IntelNasdaq: INTC: Designs and manufactures microprocessors and semiconductor components.
5+ YOEBachelor's/Master's in Electrical/Computer Engineering; 5+ years CPU circuit/backend design; 5+ years circuit design and STA; strong PPA tradeoff and debug skills.
Verilog, SPICE, Timing Analysis, Circuit Simulation
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ASIC Physical Design Engineer
Maynard or Austin
$136k-$195k/yr HybridFull Time
Cisco
CiscoNASDAQ: CSCO: Develops and sells networking hardware and cybersecurity software.
5+ YOEBachelors in Engineering with 5+ years or Masters in Engineering with 3+ years in ASIC physical design; experience with floorplanning, place-and-route, STA, timing closure, DFT collaboration, scripting, and design flow optimization.
Cadence Innovus, Synopsys ICC2, Synopsys DC/FC, Synopsys Formality, Cadence LEC, Tempus, Python, TCL, Perl
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Senior Silicon Engineer
Redmond or Austin or Raleigh or Hillsboro
$120k-$235k/yr HybridFull Time
Microsoft
MicrosoftNASDAQ: MSFT: Develops software, services, devices, and cloud computing solutions.
1+ YOEDegree in EE/CE/CS or equivalent with 1–5+ years technical engineering experience depending on degree; expertise in RTL, synthesis, STA, PD flows; proficiency in Tcl and Python; ability to pass Microsoft cloud background and export-control screenings.
PrimeTime, Genus, DC, Innovus, ICC2, Tcl, Python
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1w
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ASIC Engineer, Implementation - Timing
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
Meta
MetaNASDAQ: META: Develops social networking platforms and virtual reality technologies.
6+ YOEBachelor's degree or equivalent,6+ years timing analysis experience, STA and timing-constraint development, knowledge of front-end and back-end ASIC flows, and cross-team communication skills.
PrimeTime, DMSA, Fusion Compiler, Innovus, Design Compiler, Genus
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3mo
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Physical Design Engineer, PnR
Austin or Fort Collins or Santa Clara
$100k-$500k/yr HybridFull Time
Tenstorrent
Tenstorrent: Designs and manufactures AI processors and RISC-V CPU solutions.
Synthesize, PNR, and STA for AI SoC partitions; use Synopsys tools; collaborate in a small PD team; knowledge of UPF/power domains and IP integration is a plus.
Synopsys Design Compiler, Fusion Compiler, IC Compiler II, Power domain tools, LEC/Formality, DRC/LVS, EM/IR, UPF, DFT (OCC/MBIST)
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Senior Staff Engineer, Physical Design (Floorplanning)
Austin, Texas, United States
$180k-$270k/yr OnsiteFull Time
Samsung Electronics
Samsung ElectronicsKorea Exchange: 005930: Develops and manufactures consumer electronics, semiconductors, and mobile devices.
11+ YOE7+ years hands-on physical-design experience; expertise in floorplanning, power-grid design, PNR flows, STA, physical verification; strong scripting and automation skills; leadership and mentoring experience.
FusionCompiler, Innovus, RedHawk, PrimeTime, Tempus, StarRC, Synopsys, Cadence, Python, Tcl, Shell, Perl
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1mo
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Senior Digital Design Engineer
Austin, Texas, United States
OnsiteFull Time
NXP Semiconductors
NXP SemiconductorsNASDAQ: NXPI: Designs and manufactures semiconductors for automotive and IoT applications.
4+ YOEBachelors in EE/CE/CS required, 4+ years IP or SoC design experience, expert Verilog, knowledge of SoC architecture, experience with Lint/CDC/STA, ARM AMBA desired; C and scripting (Perl/Python) and functional safety are a plus.
Verilog, System Verilog, Lint, CDC, Static Timing Analysis (STA), ARM AMBA, C, Perl, Python
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Infrastructure and Tools Developer
Austin, Texas, United States
OnsiteFull Time
Ericsson
EricssonNasdaq Stockholm: ERIC B: Global provider of telecommunications equipment and services.
Several years of ASIC/SoC frontend experience with RTL/Verilog/SystemVerilog,UVM; scripting in Perl/Python/bash/csh; familiarity with synthesis, STA, DFT and front-end verification tools; BS/MS in EE/CS.
Verilog, UVM, SystemVerilog, Perl, Python, bash, csh, CloudBees Jenkins, LSF (Load Sharing Facility), Slurm, Altair
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Infrastructure and Tools Developer (787687)
Austin, Texas, United States
HybridFull Time
Ericsson
EricssonNasdaq: ERIC: Manufactures telecommunications equipment and provides networking services.
Hands-on experience with ASIC/SoC design, RTL, Verilog, UVM/SystemVerilog, front-end EDA tools, synthesis/STA/DFT, and scripting (Perl, Python, bash, csh). Strong communication and presentation skills.
Verilog, UVM, SystemVerilog, Perl, Python, bash, csh, CloudBees Jenkins, Load Sharing Facility (LSF), Slurm, Altair
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1mo
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Digital Design Verification Engineer
Bristol or Austin
£125k/yr OnsiteFull Time
Olix
Olix: Developing optical hardware for artificial intelligence inference.
5+ YOE5+ years in digital verification for high-performance ASICs/SoCs; strong SystemVerilog, SVA, UVM, Cocotb, formal verification, CDC/RDC, and algorithm modelling (MATLAB/Simulink or Python/NumPy) skills; experience with high-speed IP (SerDes, DDR/HBM, PCIe).
SystemVerilog, UVM, SVA, CocoTB, MATLAB/Simulink, Python, NumPy, Jasper, FPGA, RTL simulation, formal verification, linting, CDC/RDC, STA, UPF, CPF, gate-level simulation
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Senior ASIC Physical Design Engineer, Netlisting
Santa Clara or Austin
$136k-$265k/yr HybridFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs GPU-accelerated computing and artificial intelligence hardware.
3+ YOE5+ years (BS) or 3+ years (MS) experience in physical ASIC design, expertise in equivalence checking/FV, RTL/logic design, CDC/MTBF analysis, logic synthesis, STA and timing convergence, and scripting/programming skills.
Perl, TCL, Make, Python, Static Timing Analysis (STA)
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2mo
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Member of Technical Staff, Hardware, Physical Design Engineer
Palo Alto or Austin
$200k-$420k/yr OnsiteFull Time
River AI
River AI: Building user-controlled, personalized AI with integrated local hardware.
5+ YOEBachelor's in EE/CE and 5+ years with advanced process nodes (7nm or below); hands-on experience with physical design, synthesis, P&R, STA, sign-off flows, UPF/CPF power intent, and scripting (Tcl/Python).
Innovus, Fusion Compiler, PrimeTime, RedHawk, Unified Power Format (UPF), Common Power Format (CPF), Tcl, Python
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1mo
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Physical Design Engineer - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine Learning
Cupertino or Austin
$136k-$213k/yr OnsiteFull Time
Amazon
AmazonNASDAQ: AMZN: Global online retail and cloud computing technology provider.
1+ YOEDegree in EE/CS with relevant experience (BS+6 / MS+4 / PhD+2), 1+ years STA and timing constraint development, scripting (Tcl/Perl/Python), timing analysis fundamentals, familiarity with PrimeTime/Tempus and RTL-to-GDSII physical design flow.
PrimeTime, Tempus, PT-DMSA, Tempus-ECO, Tweaker, STAR-RC, Quantus, SPICE, SPECTRE, Tcl, Perl, Python
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