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99 sta engineer jobs at 31 companies in San Jose, CA

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STA Engineer
Santa Clara, California, United States
$153k-$230k/yr OnsiteFull Time
Qualcomm
QualcommNASDAQ: QCOM: Designs and manufactures semiconductors and wireless telecommunications products.
6+ YOE6+ years ASIC/SoC STA and synthesis experience with timing-closure, MMMC, low-power checks, SDC development, scripting (TCL/Perl), and hands-on use of PrimeTime and synthesis tools.
TCL, Perl, Python, Synopsys Prime Time, Synopsys Design Compiler, Cadence Genus, Conformal ECO Tool, PrimePower (PTPX)
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3mo
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Senior Static Timing Analysis (STA) Methodology Engineer
Saratoga, California, United States
$120k-$220k/yr OnsiteFull Time
E-Space
E-Space: Builds sustainable LEO satellite networks for global IoT connectivity
8+ YOESenior STA/Timing methodology engineer with 8+ years in STA, scripting (Tcl/Python/Perl), signoff; BS/MS in ECE or related; onsite in Saratoga, CA.
PrimeTime, PT-SI, PT-PX, PT-ECO, Tcl, Python, Perl
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ASIC DFT STA Engineer
San Jose or Santa Clara
$165k-$241k/yr OnsiteFull Time
Cisco
CiscoNASDAQ: CSCO: Develops and sells networking hardware and cybersecurity software.
1+ YOEDegree plus relevant years of experience (BSc+7 / MSc+4 / PhD+1). Experience with RTL, CDC/RDC, conformal verification, SDC development, timing constraint development, and scripting (Perl, Tcl, Python, Makefile).
Perl, Tcl, Python, Makefile, Synopsys TCM, Synopsys PrimeTime, Synopsys Fusion, Synopsys Design Compiler, Tessent, Conformal
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3w
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STA/Constraints Engineer
Santa Clara, California, United States
HybridFull Time
AMD
AMDNASDAQ: AMD: Designs and manufactures computer processors and graphics technology.
Experience in STA, timing signoff, and physical design; expert use of PD tools (SNPS PT/GCA, ICC2/FC); scripting with Perl/TCL/Shell/Python; Verilog RTL experience; strong communication; Bachelor/Master preferred.
SNPS PT, GCA, ICC2, FC, Perl, TCL, Shell, Python, Verilog, SDC
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4w
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ASIC Implementation Engineer STA
San Jose, California, United States
$144k-$230k/yr OnsiteFull Time
Broadcom
BroadcomNASDAQ: AVGO: Designs and sells semiconductors and infrastructure software to enterprises.
12+ YOEBachelor's in EE or Computer Engineering, 12+ years ASIC STA experience, proficiency with Cadence or Synopsys sign-off flows, SDC/constraint development, and scripting in Tcl, Python, or Perl.
Tcl, Python, Perl, Shell, Cadence, Synopsys
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2w
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Static Timing Analysis Engineer, Full Chip STA
Mountain View, California, United States
$163k-$236k/yr OnsiteFull Time
Google
GoogleNASDAQ: GOOGL: Provides online search, advertising, cloud computing, and consumer electronics.
8+ YOEBachelor's in EE/CS or equivalent,8+ years in silicon timing closure and chip integration, experience with PrimeTime/Tempus, STA signoff and constraint authoring, scripting with Tcl or Perl.
PrimeTime, Tempus, Tcl, Perl
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Sr. Staff Physical Design Timing Engineer (STA)
Boston or Mountain View or Toronto
$217k-$267k/yr HybridFull Time
Lightmatter
Lightmatter: Develops photonic processors and interconnects for AI data centers
12+ YOEBachelor's in EE/CE, 12 years physical design experience (minimum 5 years hands-on ASIC STA/timing closure), experience with Cadence or Synopsys flows, Tempus/PrimeTime, scripting (TCL, Python, PERL, Shell), strong problem-solving and communication.
Tempus, PrimeTime, Cadence, Synopsys, TCL, Python, PERL, Shell
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Principal Physical Design Engineer, STA
San Jose, California, United States
$209k-$250k/yr OnsiteFull Time
Astera Labs
Astera LabsNASDAQ: ALAB: Designs connectivity solutions for cloud and AI infrastructure.
10+ YOE10+ years in timing analysis and sign-off for complex SoCs; Cadence/Synopsys flows; 7nm or below; scripting (Tcl/Python/Perl); able to work independently.
Cadence, Synopsys, Tcl, Python, Perl, SystemVerilog
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Physical Design Implementation and STA Lead
San Jose, California, United States
$149k-$215k/yr OnsiteFull Time
Altera
Altera: Manufacturer of field-programmable gate arrays and programmable logic devices.
7+ YOEBachelor's in EE/CE,7+ years physical design/implementation experience,3+ years STA with Synopsys PrimeTime,block-level implementation skills,Proficiency in Tcl and Python,mentoring and leadership experience.
Synopsys PrimeTime, Tcl, Python
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Senior ASIC Timing Engineer
Santa Clara or Durham or Austin or Hillsboro
$136k-$265k/yr HybridFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs graphics processing units and artificial intelligence hardware.
3+ YOEBS in ECE + 5 years or MS + 3 years in timing/STA; hands-on full-chip and sub-chip STA, timing convergence, ECO implementation, physical design optimization, and deep sub-micron modeling.
STA, RTL, DFT, DFX, Formal Verification (FV)
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Senior DFT Engineer
Santa Clara, California, United States
$136k-$265k/yr HybridFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs GPU-accelerated computing and artificial intelligence hardware.
3+ YOEExperience in scan test, BIST, ATPG, fault simulation; strong scripting (Perl/Python/Tcl); cross-functional RTL, STA, PnR exposure; silicon bring-up and ATE experience.
Perl, Python, Tcl, ATPG, STA, ATE
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Physcial Design Engineer
Mountain View, California, United States
$100k-$180k/yr OnsiteFull Time
Wipro
WiproNYSE: WIT: Global technology services and consulting for digital transformation.
8+ YOERequires 8–10 years of physical design and PnR experience, advanced-node expertise, and proficiency with floorplanning, CTS, routing, timing closure, STA, SDC, EMIR, PPA optimization, and EDA tools.
Synopsys Fusion Compiler, Synopsys ICC2, PrimeTime, Cadence Innovus, RedHawk, Voltus, GDSII, SDC, STA, EMIR
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2mo
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SoC Design Engineer
Santa Clara, California, United States
$157k-$160k/yr OnsiteFull Time
OMNIVISION
OMNIVISIONHong Kong Stock Exchange: 0501: Designs and develops advanced imaging and display semiconductor solutions.
1+ YOEMaster's in Electrical or Computer Engineering required, 1+ year digital design experience; RTL/Verilog, SystemVerilog/SVA, Python, Perl; experience with Synopsys PrimeTime, Cadence Virtuoso, Design Compiler, Integrator; FPGA prototyping, STA, DFT.
Synopsys PrimeTime, Cadence Virtuoso, Design Compiler, Integrator, SystemVerilog, SVA, Python, Perl, Verilog, FPGA
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Principal Physical Design Engineer
Redmond or Mountain View or Santa Clara or Hillsboro or Austin or Boise or Raleigh
$143k-$275k/yr HybridFull Time
Microsoft
MicrosoftNASDAQ: MSFT: Develops software, services, devices, and cloud computing solutions.
3+ YOEDegree in EE/Computer Engineering/CS or equivalent experience with 3+ years (PhD),6+ years (MS) or 8+ years (BS) technical engineering experience; expertise in PnR, STA, PV, timing ECOs; scripting in TCL/Python; pass security and export screenings.
Synopsys Fusion Compiler, PrimeClosure, Primetime, Formality, VCLP, Star-RC, Redhawk SC, Cadence Innovus, Siemens Calibre, TCL, Python
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3w
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Physical Design Engineer (PD/PnR)
Sunnyvale or Mountain View
$45k-$121k/yr OnsiteFull Time
Wipro
WiproNew York Stock Exchange: WIT: Global provider of IT consulting and business process services.
3+ YOERequires 3–5 years of physical design and PnR experience, a bachelor's or master's degree in electrical or computer engineering, Fusion Compiler expertise, STA/MMMC, low-power flows, and Tcl, Perl, or Python scripting.
Synopsys Fusion Compiler, Static Timing Analysis (STA), UPF, Tcl, Perl, Python, DRC, LVS
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4w
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Sr. / Staff ASIC Digital Design Engineer
San Jose, California, United States
OnsiteFull Time
SK hynix Memory Solutions America
SK hynix Memory Solutions AmericaKorea Exchange: 000660: Develops semiconductor controllers and firmware for enterprise data storage.
6+ YOEExpertise in DFT, synthesis, power and timing analysis; tapeout experience; scripting (tcl/perl/python/shell); UPF and STA; Bachelors+8 years or Masters+6 years in engineering.
Synopsys, Siemens Tessent, PT, DC, VCLP, Formality, LEC, PrimeClosure, PrimePower, VCS, VC-spyglass-dft, Tetramax, Tessent, UPF, UNIX, Linux, tcl, perl, python, shell
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2mo
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EDA Tools Hardware Engineer
Santa Clara or Folsom or Hillsboro or Austin
$142k-$269k/yr HybridFull Time
Intel
IntelNasdaq: INTC: Designs and manufactures microprocessors and semiconductor components.
2+ YOEDegree in computer/electrical engineering or CS plus relevant experience; expertise in physical design (placement, routing), clock tree synthesis, Innovus-based full‑chip integration; Linux scripting and STA/power analysis preferred.
Innovus, Linux
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2w
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ASIC Engineer, Implementation - Timing
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
Meta
MetaNASDAQ: META: Develops social networking platforms and virtual reality technologies.
6+ YOEBachelor's degree or equivalent,6+ years timing analysis experience, STA and timing-constraint development, knowledge of front-end and back-end ASIC flows, and cross-team communication skills.
PrimeTime, DMSA, Fusion Compiler, Innovus, Design Compiler, Genus
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3mo
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Physical Design Engineer, PnR
Austin or Fort Collins or Santa Clara
$100k-$500k/yr HybridFull Time
Tenstorrent
Tenstorrent: Designs and manufactures AI processors and RISC-V CPU solutions.
Synthesize, PNR, and STA for AI SoC partitions; use Synopsys tools; collaborate in a small PD team; knowledge of UPF/power domains and IP integration is a plus.
Synopsys Design Compiler, Fusion Compiler, IC Compiler II, Power domain tools, LEC/Formality, DRC/LVS, EM/IR, UPF, DFT (OCC/MBIST)
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RTL Engineer
Mountain View, California, United States
$250k-$375k/yr OnsiteFull Time
DensityAI
DensityAI: Designing custom AI hardware accelerators for large language models.
5+ YOE5+ years RTL/SoC design to silicon, expert Verilog/SystemVerilog, synthesis/timing/CDC/SDC awareness, microarchitecture skills, collaboration across DV/PD/DFT, and scripting in Python/Tcl.
SystemVerilog, Verilog, Python, Tcl, SDC, STA, UPF, HBM, PCIe, SerDes, RISC-V, FPGA
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