3mo
Save
Mark Applied
Hide
SOC Physical Design Static Timing Analysis Engineer
Phoenix or Santa Clara
$164k-$312k/yr HybridFull Time
7+ YOEBachelor's/Master's/PhD in EE/CE/CS; 7+ yrs SOC timing analysis; 3+ yrs tools; TCL scripting; timing constraints; clock network; PVT; cross-team collaboration.
Timing Analysis Tools, Extraction Tools, Physical Design Tools, TCL Scripting
1mo
Save
Mark Applied
Hide
Senior CPU RTL Design Engineer – Power Management
Austin or Phoenix
$164k-$269k/yr HybridFull Time
7+ YOEBachelor's (9+ years) or Master's (7+ years) in ECE/CE/CS. Experience in low-power CPU/SoC RTL design, power management (DVFS, power states), RTL development (Verilog/SystemVerilog), debug and system-level design. Preferred: CDC, static timing analysis, UPF, lint.
SystemVerilog, Verilog, x86 assembly, CDC, UPF, static timing analysis, lint