23 uvm jobs at 10 companies in Coolidge, AZ
2mo
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Senior CPU Design Verification Engineer
Austin or Phoenix
$142k-$200k/yr HybridFull Time
4+ YOE4+ years in design verification; SystemVerilog/UVM; pre-silicon CPU/SoC verification; strong debugging; Bachelor's or Master in Electrical or Computer Engineering.
SystemVerilog, UVM, EDA tools, Python, Linux
3mo
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Senior Technical Staff Engineer - Verification
Chandler, Arizona, United States
OnsiteFull Time
15+ YOESenior verification engineer with 15+ years in functional verification; expert in SystemVerilog, UVM, and formal verification for IP/SoC; strong debugging and cross-functional collaboration.
SystemVerilog, UVM, Formal Verification, IP-level verification, SoC verification, ARM/RISC architectures
1w
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Director, Digital Design & Verification
Chandler, Arizona, United States
OnsiteFull Time
Proven leader in digital IC design and verification for mixed-signal SoCs with expertise in RTL, verification methodologies (UVM, formal, AMS/DMS), architecture, and team building.
SystemVerilog, UVM, Formal, AMS/DMS, RTL, STA, DFT
1mo
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Staff Design Verification Engineer (AI/ML)
Chandler, Arizona, United States
OnsiteFull Time
5+ YOEMS EE/CE with 7+ years or PhD with 5+ years (BSEE/BSCE considered); strong SystemVerilog/UVM and Python skills; experience delivering verification to tape-out; knowledge of formal verification and CDC; familiarity with Xcelium and JasperGold.
SystemVerilog, UVM, Python, Xcelium, JasperGold, Verilog-AMS, SDF
1mo
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Senior Design Verification Engineer (eInfochips Inc)
Minneapolis or Phoenix
OnsiteFull Time
Bachelor’s or Master’s in EE/CE or related; strong SystemVerilog and UVM skills; scripting with Python/Perl/Tcl; experience with Cadence Xcelium, Synopsys VCS or Siemens Questa; knowledge of constrained-random verification, SVA, functional coverage and AMBA protocols.
UVM, SystemVerilog, Python, Perl, Tcl, Cadence Xcelium, Synopsys VCS, Siemens Questa, Cadence Palladium, C, SVA, UPF, CPF, Real Number Models (RNM), AMBA (AXI/AHB/APB)
2mo
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Advanced ASIC FPGA Verification Engineer for Crypto and Cross Domain Solutions
Scottsdale, Arizona, United States
$135k-$150k/yr OnsiteFull Time
3+ YOEBachelor's in ECE/CS/math plus 5 years or Master's plus 3 years; DoD Secret clearance required; strong SystemVerilog, VHDL, UVM, coverage-driven verification, protocol and CDC knowledge; simulation and CI/CD experience.
SystemVerilog, VHDL, UVM, QuestaSim, ModelSim, Xilinx Vivado Design Suite, Questa CDC, Jenkins, GitLab CI, GitHub Actions, Python, Tcl, Bash, Perl, Git, Questa verification IP (QVIP)
1mo
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Senior Design Verification Engineer
Tempe or Independence or Arizona or Ohio or San Jose or New York City
$142k-$224k/yr HybridFull Time
8+ YOE8+ years design verification experience with UVM and testbench development; Bachelor's in EE/CE or related; experience with Questa/Xcelium/VCS; AI/agentic DV experience preferred; US citizenship and ability to obtain Secret clearance; travel up to 10%.
UVM, SystemVerilog, VHDL, Verilog, Questa, Xcelium, VCS, Jira
5d
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Senior Design Verification Engineer
Tempe or Independence
$156k-$291k/yr RemoteFull Time
8+ YOE8+ years design verification experience with UVM, SystemVerilog, RTL verification for FPGA/ASIC, Bachelor's in EE/CE, US citizenship, ability to obtain Secret clearance, familiarity with Questa/Xcelium/VCS and AI verification tools.
Universal Verification Methodology (UVM), SystemVerilog, VHDL, Verilog, Questa, Xcelium, VCS, Jira
1w
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FPGA Digital Engineer - 2
Chandler, Arizona, United States
$87k-$131k/yr OnsiteFull Time
2+ YOEBachelor's in EE/CE plus 2 years (or Master's), ability to obtain DoD Secret clearance, FPGA (VHDL/Verilog) experience, Vivado and simulation tool familiarity, and digital interface verification experience.
VHDL, Verilog, AMD Xilinx FPGAs, Vivado IDE, Questa, ModelSim, Vitis Unified IDE, C, C++, OSVVM, UVM
1mo
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Analog Mixed Signal Modeling Engineer (UL - 02)
Austin or Chandler or Greensboro
HybridFull Time
Master's in EE/Computer Eng required. Experience in mixed-signal product development, analog IC design, SystemVerilog RNM, AMS simulators, verification methodologies, and strong analytical and communication skills.
SystemVerilog Real Number Modeling (SV-RNM), Verilog AMS, AMS simulators, System Verilog Assertions, PSL Assertions, Perforce, GIT, UVM, Simulink, Simscape, Python
1w
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Principal FPGA Digital Engineer - 3
Chandler, Arizona, United States
$108k-$162k/yr OnsiteFull Time
5+ YOEAble to obtain DoD Secret clearance; 5+ years FPGA/SoC design experience (VHDL/Verilog) with Xilinx devices, Vivado flow, simulation and hardware debug; Bachelor in EE/CE or advanced degree with equivalent experience.
VHDL, Verilog, AMD Xilinx, Vivado IDE, Vitis Unified IDE, Questa/ModelSim, Ethernet, PCIe, AXI4, UART, SDLC, DDR3, DDR4, DDR5, OSVVM, UVM, C, C++, Logic Analyzer, Oscilloscope
4w
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Applications Engineer - FPGA Prototyping
San Diego or Austin or Boulder or Costa Mesa or Pasadena or Tempe or Wilsonville or Fremont
$167k-$334k/yr HybridFull Time
5+ YOE5+ years in design/verification/FPGA/ASIC or similar; BS/MS in EE/CE/CS; active experience with SystemVerilog/Verilog/VHDL, FPGA tools, scripting, simulation and customer-facing technical support.
SystemVerilog, Verilog, VHDL, SystemC, C/C++, Perl, Python, XML, JSON, proFPGA, HAPS, Xilinx Vivado, Altera Quartus, Questa, Incisive, VCS, OVM, UVM