36 uvm jobs at 15 companies in Los Angeles, CA
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Principal Design Verification Engineer (Silicon Engineering)
Irvine or Austin or Redmond or Sunnyvale
$210k-$300k/yr OnsiteFull Time
10+ YOEBachelor in ECE/CS and 10+ years in design verification; strong UVM/OVM/VMM, Python, and RTL/ASIC/FPGA experience.
UVM, OVM, VMM, Python, RTL, ASIC, FPGA, constrained random verification
1mo
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FPGA Verification Engineer, Air Dominance and Strike (Fastwater Staffing)
Costa Mesa, California, United States
RemoteFull Time
2+ YOEBachelor's in EE/CE, 2+ years FPGA/ASIC verification, proficient in SystemVerilog/UVM/SVA, experience with industry simulators, Git and Linux, eligible for U.S. Secret clearance.
SystemVerilog, UVM, SVA, Questa, VCS, Xcelium, Vivado, Git, Linux, SVUnit, Python, Tcl, Makefile, Nix
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FPGA Verification Engineer, Air Vehicles
Costa Mesa, California, United States
$123k-$171k/yr OnsiteFull Time
2+ YOEBachelor's in EE/CE, 2+ years FPGA/ASIC verification, proficient in SystemVerilog, UVM, SVA, industry simulators, Git, Linux; eligible to obtain U.S. Secret clearance.
SystemVerilog, UVM, SVA, Questa, VCS, Xcelium, Vivado, Git, Linux, Python, Tcl, Makefile, SVUnit, Nix
3mo
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Sr. Satellite Design Verification Engineer, Amazon Leo
Irvine or Austin or Sunnyvale or Redmond or San Diego
OnsiteFull Time
7+ YOEBachelor's in Electrical/Communications Engineering; 3+ years UVM/SystemC/DPI-C; 7+ years verification in communications; preferred advanced degree; Matlab familiarity; DV/integration experience.
UVM, C, SystemC, DPI-C, Matlab
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Wireless SOC Verification Engineer
Irvine, California, United States
OnsiteFull Time
Experience verifying complex SoCs using UVM testbenches, developing coverage-driven and directed tests, deploying AI tools, and collaborating across product teams to improve tape-out readiness.
UVM
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Design Verification Engineer
Aliso Viejo or San Jose or Córdoba or Toronto
OnsiteFull Time
3+ YOEBachelors in EE/CE/CS,3+ years verification experience, SystemVerilog/UVM, coverage-driven verification, C/C++ and scripting (Python,Tcl,Perl),test planning and debug skills.
SystemVerilog, UVM, C, C++, Python, Tcl, Perl
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Design Verification Engineer
Broomfield or San Diego or Fort Collins or San Jose or Irvine
$144k-$230k/yr OnsiteFull Time
10+ YOE12+ years verification experience for complex digital and mixed-signal circuits; proficiency with SystemVerilog/UVM/SVA, scripting, simulation tools, and RTL/gate-level debug; BS/MS in EE/CE.
SystemVerilog, UVM, SVA, Synopsys, Cadence, Mentor, Perl, Python, Tcl, DesignSync, git, Palladium, Veloce, Zebu, Xilinx, ICL, PDL, Tessent
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Senior ASIC Design Verification Engineer - Terawave
Los Angeles or Seattle or California or Washington or Texas or United States
$230k-$323k/yr RemoteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
8+ YOEBS/MS in EE/CE, 8+ years ASIC/SoC verification experience, deep System Verilog and UVM expertise, verification planning, coverage closure, RTL/debugging, cross-functional collaboration.
System Verilog, UVM, RTL
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Senior Staff Digital Design Engineer
Irvine, California, United States
$136k-$201k/yr OnsiteFull Time
Bachelor's degree in EE/CE/CS, RTL development with Verilog/SystemVerilog, synthesis/timing/CDC/low-power checks, debug via simulation/emulation/FPGA/silicon, verification/UVM preferred, mentoring and sub-circuit ownership experience.
Verilog, SystemVerilog, UVM, FPGA
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Principal ASIC Design Verification Engineer
United States or Los Angeles
$190k-$285k/yr OnsiteFull Time
10+ YOEB.S. or M.S. in EE/CE or related, 10+ years ASIC/SoC verification, strong SystemVerilog/UVM and SVA skills, experience with VCS/Xcelium/Questa and Verdi/SimVision, scripting (Python/Perl/TCL), Git, CI/CD, C/C++, and ITAR U.S. person eligibility.
SystemVerilog, UVM, SystemVerilog Assertions (SVA), VCS, Xcelium, Questa, Verdi, SimVision, Python, Perl, TCL, Git, C, C++, CI/CD
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FPGA Engineer II
Long Beach, California, United States
$102k-$141k/yr OnsiteFull Time
2+ YOEBachelor’s degree in engineering, 2+ years of FPGA firmware development, VHDL proficiency, FPGA design fundamentals, and U.S. citizenship or required export authorization.
VHDL, Xilinx, Microchip, UVM, VUnit, SPI, UART, I2C, CAN, GigE, PCIe, GIT, JIRA, PCB
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Senior ASIC/FPGA Verification Engineer (Onsite)
El Segundo or Fullerton
$96k-$182k/yr OnsiteFull Time
5+ YOEActive transferable U.S. SECRET clearance and U.S. citizenship, STEM degree (BS or advanced) with 5+ years (BS) or 3+ years (advanced) experience, RTL verification using VHDL/Verilog/SystemVerilog, testbench and coverage, and revision control (Git/Subversion).
SystemVerilog, OVM, UVM, VHDL, Verilog, Git, Subversion, QuestaSim, Synplify, Quartus, Vivado, Unix, Linux
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Senior Principal Digital Engineer
Woodland Hills, California, United States
$156k-$235k/yr OnsiteFull Time
4+ YOEU.S. citizen with active Secret clearance; STEM degree (BS/MS/PhD) with relevant experience (min 4+ yrs depending on degree); experience in high-speed digital design, FPGA/SoC/ASIC (VHDL/Verilog), design verification, and hardware implementation.
VHDL, Verilog, System Verilog, UVM, FPGA, SOC, ASIC, MATLAB, Simulink, Hardware-In-Loop, DO-254
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Applications Engineer - FPGA Prototyping
San Diego or Austin or Boulder or Costa Mesa or Pasadena or Tempe or Wilsonville or Fremont
$167k-$334k/yr HybridFull Time
5+ YOE5+ years in design/verification/FPGA/ASIC or similar; BS/MS in EE/CE/CS; active experience with SystemVerilog/Verilog/VHDL, FPGA tools, scripting, simulation and customer-facing technical support.
SystemVerilog, Verilog, VHDL, SystemC, C/C++, Perl, Python, XML, JSON, proFPGA, HAPS, Xilinx Vivado, Altera Quartus, Questa, Incisive, VCS, OVM, UVM
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FPGA Engineer II
Long Beach, California, United States
$102k-$141k/yr OnsiteFull Time
2+ YOEBachelor's degree in engineering, 2+ years of FPGA firmware development, VHDL proficiency, FPGA design knowledge, and U.S. citizenship or required authorization.
VHDL, Xilinx, Microchip, UVM, VUnit, SPI, UART, I2C, CAN, GigE, PCIe, GIT, JIRA
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Senior Principal Digital Design Engineer
Irvine, California, United States
$186k-$228k/yr OnsiteFull Time
6+ YOEExpert digital ASIC design experience, SystemVerilog/RTL implementation, block/system verification, synthesis/power/timing analysis, and technical leadership; BS in EE (or advanced) plus extensive experience.
SystemVerilog, Verilog, UVM, SystemC, PCIe, PCI-SIG, IEEE 802.3, SDC
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Firmware Engineer
Irvine, California, United States
$145k-$175k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE,5+ years FPGA firmware experience with VHDL/Verilog,3+ years Xilinx tool experience,SoC/PS-PL integration,FPGA DSP implementation,EMB Linux/bare-metal familiarity,strong verification and debug skills.
VHDL, Verilog, Vivado, Vitis, Vivado HLS, UVM, Git, oscilloscope, logic analyzer, spectrum analyzer
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