345 uvm jobs at 81 companies in California
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SoC Verification Engineer – NoC / UVM
San Jose, California, United States
$146k-$250k/yr HybridFull Time
Expertise in SystemVerilog and UVM, ASIC/SoC verification, constraint-random and coverage-driven methodologies, formal verification (SVA); experience with Synopsys VCS and Cadence IES preferred; B.S. or M.S. in computer/electrical engineering.
SystemVerilog, UVM, OVM, VMM, Verilog, SystemVerilog Assertions (SVA), Synopsys VCS, Cadence IES, Cadence IEV, Jasper, Synopsys VC-Formal, Magellan
3w
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SoC Verification Engineer
Austin or Santa Clara or Hillsboro
$142k-$200k/yr HybridFull Time
3+ YOE3+ years SoC design verification experience (4+ with bachelor's) with OVM/UVM, AMBA protocols, UVM testbench creation, debugging, and test planning; bachelor's or master's in EE/CE/CS or related.
OVM, UVM, CHI, AXI, AHB, APB, VIP, emulation models, system simulation tools
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ASIC Design Verification Technical Lead, TPU
Sunnyvale, California, United States
$192k-$278k/yr OnsiteFull Time
10+ YOE10+ years verif. experience with UVM/SystemVerilog; lead verification and testbench development.
SystemVerilog, UVM, Python, Perl, Shell, Bash, Linux
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Design Verification Engineer - Viasat Government
Marlborough or Carlsbad
$133k-$210k/yr OnsiteFull Time
5+ YOEBachelor's in Electrical or Computer Engineering; 5+ years hardware verification with SystemVerilog/UVM; RTL verification; strong SystemVerilog/UVM; experience with industry EDA tools; US citizenship and active Secret clearance; willingness to travel up to 10%
SystemVerilog, UVM, Siemens Questa, Cadence, Synopsys, Mentor, Python, TCL
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Staff DV Engineer
Saratoga, California, United States
$120k-$220k/yr OnsiteFull Time
6+ YOE6+ years design verification in semiconductor; Verilog/SystemVerilog; UVM; C/C++; Python; leadership experience.
Verilog, SystemVerilog, UVM, C, C++, Python, VHDL
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R&D Engineer IC Design
San Jose, California, United States
$120k-$192k/yr OnsiteFull Time
6+ YOE6+ years in design verification; master’s in ECE/CS; SystemVerilog, scripting; UVM preferred; knowledge of networking and switching.
SystemVerilog, UVM, Scripting, Testbenches, ATE testing
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Lead ASIC Design Verification Engineer, Amazon Leo
San Diego or Sunnyvale or Redmond
$159k-$215k/yr OnsiteFull Time
7+ YOEMaster's or PhD in Electrical Engineering; 7+ years verification experience; 5+ years in UVM, C/C++, and scripting.
UVM, C/C++, SystemC, DPI-C, Matlab, Scripting
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Design Verification Engineer
Mountain View, California, United States
$120k-$475k/yr HybridFull Time
Concept-to-silicon verification experience with SystemVerilog, UVM, ABV, and scripting; production verification and silicon bring-up experience preferred.
SystemVerilog, Python, C/C++, Bluespec, UVM, assertion-based verification (ABV)
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Principal Design Verification Engineer (Silicon Engineering)
Irvine or Austin or Redmond or Sunnyvale
$210k-$300k/yr OnsiteFull Time
10+ YOEBachelor in ECE/CS and 10+ years in design verification; strong UVM/OVM/VMM, Python, and RTL/ASIC/FPGA experience.
UVM, OVM, VMM, Python, RTL, ASIC, FPGA, constrained random verification
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Senior ASIC Verification Engineer
San Jose, California, United States
RemoteFull Time
8+ YOE8+ years in networking hardware verification; UVM/SystemVerilog; RTL debugging; complex SoCs; Git/SVN; BS in CE/CS/EE.
UVM, SystemVerilog, VCS, Verdi, Git, SVN, Python, TCL, Perl, Shell, TCP/IP, RDMA, RoCE, IPSec
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Senior Staff Design Verification Engineer – Memory Sub-System (LPDDR/DDR/HBM )
Santa Clara, California, United States
$134k-$201k/yr OnsiteFull Time
5+ YOE5-10 years ASIC/SoC verification; DDR/LPDDR/HBM; SystemVerilog/UVM; debugging; standard tools; digital design fundamentals.
SystemVerilog, UVM, DDR, LPDDR, HBM, simulation, waveform debugging, emulation
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CPU Verification Fellow, RISC-V High-Performance Processor
Santa Clara or Austin
$100k-$500k/yr HybridFull Time
Experience leading verification for high-performance CPUs; strong SystemVerilog/UVM; knowledge of RISC-V; ability to guide large engineering teams.
SystemVerilog, UVM, Constrained-Random Verification, Formal Verification, ISA, Debug Methodologies
3mo
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Mixed-Signal Verification Engineer
San Francisco Bay Area or San Diego
OnsiteFull Time
10+ YOEBS with 10+ years in RF/mixed-signal verification; UVM/SystemVerilog; HDL; Python/Matlab a plus; UPF; testbenches and DV for SOCs.
SystemVerilog, Verilog, UVM, Python, Matlab, UPF, Virtuoso, ADE, HED
1mo
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Design Verification Engineer – Physical AI Compute
Santa Clara or Austin or Boston
$75k-$275k/yr OnsiteFull Time
Experience verifying complex digital/SoC systems with SystemVerilog/UVM, C/C++, assertions, formal, emulation and debugging across HW/SW boundaries.
SystemVerilog, UVM, C, C++, formal verification, emulation, FPGA
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Senior Debug Verification Engineer
San Jose, California, United States
$149k-$215k/yr OnsiteFull Time
8+ YOE8+ years ASIC/design verification; SystemVerilog; UVM and formal verification; Linux/Unix scripting with Perl or Python; strong cross-site collaboration.
SystemVerilog, UVM, Formal verification, Linux, Perl, Python, Emulation, JTAG, PCIe, USB
3mo
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Staff Engineer, GPU Design Verification (Subsystems)
Austin or San Jose
$151k-$252k/yr OnsiteFull Time
6+ YOE6+ years in GPU/CPU/semiconductor design verification; strong SystemVerilog/UVM, C/C++, Python; testbench development; debugging and collaboration skills.
SystemVerilog, UVM, C++, Python, Perl
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Principal Engineer, ASIC Design Verification
San Jose, California, United States
$190k-$240k/yr OnsiteFull Time
12+ YOEMS in Electrical or Computer Engineering; 12+ years ASIC/SoC verification experience; SystemVerilog and UVM expert; verification environment design; scripting for automation.
SystemVerilog, UVM, Scripting (Python, Perl, Tcl, Shell)
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SOC Verification and Methodology Engineer - SCL
Santa Clara, California, United States
$153k-$230k/yr OnsiteFull Time
2+ YOEDevelop and implement SOC verification methodologies, create and execute test plans, debug issues; requires SystemVerilog/UVM experience and design verification background.
SystemVerilog, UVM, Perl, Python
3mo
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ASIC Senior Verification Engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
10+ YOE10+ years in VLSI design/verification; Verilog/SystemVerilog; UVM; Python, TCL, PERL or similar; C/C++; Bachelor’s or Master’s in Electrical or Computer Engineering.
Verilog, SystemVerilog, UVM, Python, C, C++, Specman, TCL, PERL
3mo
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ASIC Senior Verification Engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
10+ YOESenior verification engineer with 10+ years in VLSI design/verification; strong Verilog/SystemVerilog, UVM; scripting (Python, Perl, TCL); C/C++; leadership.
Verilog, SystemVerilog, UVM, Python, PERL, TCL, C, C++, Specman
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