13 uvm jobs at 8 companies in Mansfield, TX
2mo
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Design Verification Engineer - APS
Dallas, Texas, United States
OnsiteFull Time
8+ YOEBachelor's degree in electrical engineering; 8+ years of experience; strong verification skills and Python, Verilog/SystemVerilog, UVM experience.
UVM, Verilog, SystemVerilog, Python
2mo
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Principal Digital Verification Engineer
Plano, Texas, United States
OnsiteFull Time
8+ YOE8+ years in verification; MS in Electrical/Computer Engineering or equivalent; BS with 10+ years; UVM and SystemVerilog experience; DDR5 verification
UVM, SystemVerilog, Verilog, DDR5
1mo
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Sr Principal Mixed Signal Verification Engineer
Richardson, Texas, United States
OnsiteFull Time
13+ YOEMaster's in EE, 13+ years AMS design/verification experience, proficiency in UVM, Spice/Spectre, VerilogAMS, strong debugging and communication skills; Python/shell and SV assertions preferred.
UVM, TLDV UVM, RNM, VerilogAMS, Spice, Spectre, Python, shell, SV-UDN, EENET, SV Assertions
1w
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Senior Staff Digital Design Engineer
Plano, Texas, United States
HybridFull Time
5+ YOE5+ years in digital IC design with Verilog/SystemVerilog, RTL, synthesis, STA, verification, silicon debug, UVM and experience with industry EDA tools; B.Tech/M.Tech in electronics or related field.
Verilog/SystemVerilog, UVM, I²C, I3C, SPI, UART, Python, Tcl, Perl, Shell, Xcelium, Genus, SpyGlass, OneSpin/JasperGold, Innovus, PrimeTime/Tempus, DFT, ARM, AMBA (AXI/AHB/APB), Cadence Virtuoso, STA, LEC, Lint, Formal Verification
1mo
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Principal Engineer, Digital Design (IO Subsystem)
Allen, Texas, United States
OnsiteFull Time
onsemi: Designs and manufactures semiconductor solutions for power and sensing.
10+ YOEBachelor's in EE (Master's preferred), 10+ years digital IC/RTL design, expert SystemVerilog, Python, UVM, UPF/STA/timing signoff, DFT experience, and strong cross-functional collaboration.
SystemVerilog, Python, UVM, UPF, STA, DFT, AI/ML
1mo
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Senior Design Verification Engineer
Dallas, Texas, United States
OnsiteFull Time
4+ YOEExpert SystemVerilog and UVM skills, testbench development, verification planning, scripting (Python, Perl, TCL), mixed-signal verification, debugging, and technical leadership; Bachelor’s required, 4+ years relevant experience.
SystemVerilog, UVM, Python, Perl, TCL
1mo
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Sr. Mixed Signal Design Verification Manager
Richardson, Texas, United States
OnsiteFull Time
13+ YOEMaster's in EE, 13+ years AMS design/verification experience, team management experience, hands-on UVM and mixed-signal verification, Spice/Spectre and simulator expertise, strong problem-solving and communication skills.
UVM, VerilogAMS, RNM, Spice/Spectre, Python, shell, SV Assertions, SV-UDN/EENET
2mo
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Mixed-Signal Verification Engineer – Analog IP
Allen, Texas, United States
OnsiteFull Time
onsemi: Designs and manufactures semiconductor solutions for power and sensing.
6+ YOEBachelor’s or Master’s degree in Electrical Engineering or related field; 6+ years in mixed-signal or digital IC verification; SystemVerilog and UVM proficiency; Verilog-A/AMS modeling; analog IP verification within digital-on-top SoCs.
SystemVerilog, UVM, Verilog-A/AMS, analog and mixed-signal simulation tools
2mo
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Staff Design Engineer - HBM Design
Richardson, Texas, United States
OnsiteFull Time
5+ YOEBachelor's in EE/Electronics + 5 years experience. CMOS and high-speed circuit design, HBM design/verification, System Verilog/Verilog/UVM, layout extraction, Verilog-SPICE co-sim, and scripting (Python/Tcl).
FINESIM, HSPICE, VERILOG, System Verilog, UVM, Python, Tcl, SPF, SDF
2mo
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Senior Engineer, Design Verification Engineering
Dallas, Texas, United States
$117k-$166k/yr HybridFull Time
2+ YOEMaster’s in CS/CE/EE or related field with 2 years in design verification; or Bachelor’s with 4 years; strong scripting (Perl/Python); SystemVerilog/UVM;Cadence Xcelium/Synopsys VCS; analog/digital/mixed-signal circuit knowledge.
Perl, Python, SystemVerilog, UVM, Cadence Xcelium, Synopsys VCS
3w
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Utility Forester
Dallas, Texas, United States
FieldFull Time
Perform UVM inspections, identify tree/brush control needs, audit contractor work; requires practical tree work experience, tree identification skills, ISA certification (or obtain in 6–12 months), commercial pesticide applicator license, valid driver’s license, and computer proficiency.
Microsoft Word, Microsoft Excel, Microsoft Access, Microsoft Outlook, Microsoft PowerPoint
1d
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Digital IC Design Engineer - USB Products
Dallas, Texas, United States
OnsiteFull Time
2+ YOEBachelor's in Electrical/Computer Engineering, 2 years digital design experience, Verilog experience, understanding of digital logic and ASIC design flow, and strong problem-solving skills.
Verilog, System Verilog, AMS, UVM, Perl, Tcl, Python
2mo
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ASIC & FPGA Design Engineer Sr
Grand Prairie, Texas, United States
$101k-$201k/yr HybridFull Time
3+ YOEBachelor's in EE or related (Master's preferred); 3+ years FPGA design and verification experience; proficiency in VHDL/Verilog/SystemVerilog, FPGA toolsets (Vivado/Vitis), simulation (Synopsys VCS), GitLab; U.S. citizenship and ability to obtain DoD Secret clearance.
VHDL, Verilog, SystemVerilog, UVM, SystemC, Python, GitLab, Vivado, Vitis, Vitis HLS, Synopsys VCS, Synopsys EDA tools, C/C++, MATLAB/Simulink, Synopsys Synplify, NCSim, ChipScope, tcpdump, Wireshark, UltraScale