140 uvm jobs at 48 companies in Texas
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Regional Director of Operations, MidWest UVM
Austin or Shreveport or Oklahoma City or Milwaukee or Saint Paul
FieldFull Time
8+ YOE8+ years leadership in utility vegetation management, multi-state operations oversight, P&L ownership, safety and compliance expertise, strong client relationship and people development skills.
GIS, ERP
2w
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SoC Verification Engineer
Austin or Santa Clara or Hillsboro
$142k-$200k/yr HybridFull Time
3+ YOE3+ years SoC design verification experience (4+ with bachelor's) with OVM/UVM, AMBA protocols, UVM testbench creation, debugging, and test planning; bachelor's or master's in EE/CE/CS or related.
OVM, UVM, CHI, AXI, AHB, APB, VIP, emulation models, system simulation tools
2mo
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Lead CPU Design Verification Engineer, Silicon
Portland or Poughkeepsie or Austin or Mountain View
$192k-$278k/yr OnsiteFull Time
8+ YOE8+ years in verification with UVM/SystemVerilog; Bachelor's in EE/CE/CS or equivalent; experience with processor microarchitecture.
SystemVerilog, UVM, ARM ISA, Linux
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Principal Digital Verification Engineer
Austin, Texas, United States
OnsiteFull Time
8+ YOEMasters in Electrical/Computer Engineering with 8+ years or Bachelor's with 10+ years experience; experience in DDR5/DDR6 verification and UVM.
UVM, SystemVerilog, DDR5/DDR6, verification environments, testbench
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Satellite Design Verification Engineer, Amazon Leo
Austin or Sunnyvale or Redmond or San Diego
$136k-$184k/yr OnsiteFull Time
5+ YOE2+ years UVM, C, SystemC, and scripting; 5+ years verification for communication systems; Bachelor's degree in Electrical Engineering.
UVM, C, SystemC, DPI-C, SystemVerilog, Matlab
2mo
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Design Verification Engineer - APS
Dallas, Texas, United States
OnsiteFull Time
8+ YOEBachelor's degree in electrical engineering; 8+ years of experience; strong verification skills and Python, Verilog/SystemVerilog, UVM experience.
UVM, Verilog, SystemVerilog, Python
2mo
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Principal Design Verification Engineer (Silicon Engineering)
Irvine or Austin or Redmond or Sunnyvale
$210k-$300k/yr OnsiteFull Time
10+ YOEBachelor in ECE/CS and 10+ years in design verification; strong UVM/OVM/VMM, Python, and RTL/ASIC/FPGA experience.
UVM, OVM, VMM, Python, RTL, ASIC, FPGA, constrained random verification
2mo
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Staff Design Verification Engineer – Coherent Interconnect
Boston or Austin
OnsiteFull Time
7+ YOELead verification for cache-coherent interconnect; 7+ years ASIC/SoC verification; SystemVerilog/UVM expertise; strong debugging and collaboration skills.
SystemVerilog, UVM, Verilog, Python
2mo
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CPU Verification Fellow, RISC-V High-Performance Processor
Santa Clara or Austin
$100k-$500k/yr HybridFull Time
Experience leading verification for high-performance CPUs; strong SystemVerilog/UVM; knowledge of RISC-V; ability to guide large engineering teams.
SystemVerilog, UVM, Constrained-Random Verification, Formal Verification, ISA, Debug Methodologies
2w
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Design Verification Engineer – Physical AI Compute
Santa Clara or Austin or Boston
$75k-$275k/yr OnsiteFull Time
Experience verifying complex digital/SoC systems with SystemVerilog/UVM, C/C++, assertions, formal, emulation and debugging across HW/SW boundaries.
SystemVerilog, UVM, C, C++, formal verification, emulation, FPGA
2w
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DV Engineer - AI
Austin, Texas, United States
$60k-$135k/yr OnsiteFull Time
5+ YOE5+ years VLSI/HVL verification experience with SV/UVM, AMBA knowledge, testplan and coverage experience, debug skills, and AI/LLM familiarity.
SV, UVM, AMBA, System Verilog, UPF, CPF, RTL, DFT, HVL, LLMs
3mo
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Staff Engineer, GPU Design Verification (Subsystems)
Austin or San Jose
$151k-$252k/yr OnsiteFull Time
6+ YOE6+ years in GPU/CPU/semiconductor design verification; strong SystemVerilog/UVM, C/C++, Python; testbench development; debugging and collaboration skills.
SystemVerilog, UVM, C++, Python, Perl
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Staff Systems Engineer (Austin, TX, US)
Austin, Texas, United States
$114k-$220k/yr OnsiteFull Time
6+ YOEMSEE 6+ years or BSEE 8+ years with systems design; MATLAB; SystemVerilog, UVM, RNM; FPGA/ASIC design; lab equipment; RF/PLL knowledge.
MATLAB, SystemVerilog, UVM, RNM, FPGA, ASIC
3mo
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Principal Design Engineer
Austin, Texas, United States
OnsiteFull Time
Design verification expert with SV-UVM, subsystem/SOC verification, ARM-based designs, AMBA protocols, C test development, mentoring, Cadence tools a plus.
SV-UVM, ARM, AMBA, C, Cadence tools
1mo
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Senior ASIC Verification Engineer
Austin, Texas, United States
$136k-$265k/yr OnsiteFull Time
3+ YOE3+ years relevant experience, Bachelor's/Master's in Computer or Electrical Engineering (or equivalent), proficiency in System Verilog, UVM, Python, Verilog, RTL, and familiarity with VCS and Verdi.
System Verilog, UVM, Python, Verilog, RTL, VCS, Verdi
2mo
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Design Verification Engineer (Einfochips)
Austin or San Jose
OnsiteFull Time
6+ YOE6+ years in System Verilog HVL and C/C++, 6+ years in UVM; strong testbench development, debug, and verification closure; experience with DSP, scripting, and version control tools.
SystemVerilog, HVL, C, C++, UVM, SVTB, Make, Perl, Python, Bugzilla, Subversion
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Staff Verification Engineer
Austin, Texas, United States
$191k-$259k/yr HybridFull Time
5+ YOE5+ years verifying PCIe/CXL subsystems or SoCs; strong digital design and Verilog/SystemVerilog skills; UVM expertise; experience with simulation/emulation, performance analysis, and testplan creation.
SystemVerilog, Verilog, UVM, Perl, Python
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Sr Principal Mixed Signal Verification Engineer
Richardson, Texas, United States
OnsiteFull Time
13+ YOEMaster's in EE, 13+ years AMS design/verification experience, proficiency in UVM, Spice/Spectre, VerilogAMS, strong debugging and communication skills; Python/shell and SV assertions preferred.
UVM, TLDV UVM, RNM, VerilogAMS, Spice, Spectre, Python, shell, SV-UDN, EENET, SV Assertions
1mo
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Sr. Modem Design Verification Engineer
Austin, Texas, United States
$125k-$231k/yr OnsiteFull Time
5+ YOEBSEE/CE required, 5+ years digital design verification experience (modem/PHY preferred), SystemVerilog/UVM, scripting (Python/Perl), strong debugging and verification methodology skills.
SystemVerilog, UVM, SystemVerilog Assertions (SVA), Python, Perl, C/C++, MATLAB
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Sr. Modem Design Verification Engineer
Austin, Texas, United States
$125k-$231k/yr OnsiteFull Time
5+ YOEBachelors in EE/CE or related; 5+ years verification experience (modem/PHY preferred); SystemVerilog and UVM experience; scripting with Python/Perl; strong debugging and wireless/DSP knowledge.
SystemVerilog, UVM, SystemVerilog assertions (SVA), Python, Perl, C/C++, MATLAB
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