666 verification jobs at 187 companies in Brookline, MA
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Senior Verification Engineer
Wilmington, Massachusetts, United States
$110k-$152k/yr OnsiteFull Time
4+ YOE4+ years verification experience with SystemVerilog/UVM, RTL simulation and debug, scripting (Python/Perl/Tcl), SoC/processor verification, and strong analytical/debugging skills.
SystemVerilog, UVM, VCS, Xcelium, Simvision, Verdi, Questa, Python, Perl, Tcl, Linux, ARM Cortex-M, RISC-V, APB, AHB, AXI, QSPI, UART, DMA
1w
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Formal Verification Engineer
Boxborough or Austin or Boston or Santa Clara
HybridFull Time
8+ YOE8+ years design verification experience with strong focus on formal verification, proficiency with VC Formal/JasperGold, SVA, formal methods, and scripting (TCL, Python, Perl); Bachelors/Masters in CE/EE.
VC Formal, JasperGold, SystemVerilog Assertions (SVA), TCL, Python, Perl
5d
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Pharmacy Benefits Verification Specialist
Waltham, Massachusetts, United States
$25/hr OnsiteFull Time
1+ YOEConduct pharmacy and medical benefit verification, run test claims, determine authorization needs, enroll patients in copay assistance; high school diploma/GED and 1+ year pharmacy/benefit verification experience required.
CPR+, E1 check, NCPDP
2mo
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Design Verification Engineer - Viasat Government
Marlborough or Carlsbad
$133k-$210k/yr OnsiteFull Time
5+ YOEBachelor's in Electrical or Computer Engineering; 5+ years hardware verification with SystemVerilog/UVM; RTL verification; strong SystemVerilog/UVM; experience with industry EDA tools; US citizenship and active Secret clearance; willingness to travel up to 10%
SystemVerilog, UVM, Siemens Questa, Cadence, Synopsys, Mentor, Python, TCL
1mo
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Senior Formal Verification Engineer
Santa Clara or Austin or Westford or Hillsboro
$168k-$311k/yr HybridFull Time
7+ YOE7+ years experience with formal verification, strong knowledge of Verilog/System Verilog, temporal logic assertions, abstraction techniques, scripting in TCL/Perl/Python, and solid understanding of CPU/GPU architectures.
Verilog, System Verilog, temporal logic assertions, TCL, Perl, Python, Jasper Gold, VC Formal, RTL
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Member of Technical Staff, Formal Verification
Santa Clara or Boston
OnsiteFull Time
10+ YOEBachelor's or Master's in EE/CE, 10+ years ASIC/SoC verification with 7+ years formal verification, expertise in SVA and formal tools, scripting (Tcl/Python/Perl/Shell), strong debugging and leadership skills.
SystemVerilog Assertions (SVA), Cadence JasperGold, Synopsys VC Formal, Siemens Questa Formal, UVM, Tcl, Python, Perl, Shell
2w
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Senior Staff Engineer, Design Verification
Westborough, Massachusetts, United States
$151k-$223k/yr OnsiteFull Time
3+ YOEBachelor's with 5+ years or Master's/PhD with 3+ years in digital design/verification; expertise in UVM, constrained-random verification, SVA, RTL debug; C/C++ and scripting (Python/Perl); Linux experience.
UVM, SystemVerilog, SystemVerilog Assertions (SVA), C, C++, Python, Perl, Linux
2mo
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ASIC/FPGA Verification Engineer IV
Denver or Highlands Ranch or Sunnyvale or Cambridge
$124k-$246k/yr OnsiteFull Time
5+ YOEBachelors in EE (or equivalent), 5+ years FPGA/ASIC verification experience, UVM/SystemVerilog/VHDL/Verilog expertise, experience with modern verification methodologies and tools, and ability to obtain DoD Secret clearance (US citizenship required).
SystemVerilog, Universal Verification Methodology (UVM), VHDL, Verilog, Linux, Microsoft Project, JIRA, Python, OVM, VMM
2mo
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Design Verification Engineer - Viasat Government
Marlborough or Carlsbad
$133k-$210k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE or related,5+ years hardware verification experience with SystemVerilog/UVM,experience with industry EDA tools,US citizenship and active Secret clearance required,ability to travel up to 10%.
SystemVerilog, UVM, Siemens Questa, Cadence, Synopsys, Mentor, AMD/Xilinx Vivado, Altera Quartus, Microchip Libero, TCL, Perl, Python, Linux
2mo
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Staff Design Verification Engineer – Coherent Interconnect
Boston or Austin
OnsiteFull Time
7+ YOELead verification for cache-coherent interconnect; 7+ years ASIC/SoC verification; SystemVerilog/UVM expertise; strong debugging and collaboration skills.
SystemVerilog, UVM, Verilog, Python
1mo
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ASIC Design Verification Engineer
Irvine or Andover or Broomfield
$129k-$207k/yr OnsiteFull Time
3+ YOEConstrained-random design verification experience using System Verilog/UVM, coverage-driven methodologies, experience with VCS/Incisive and scripting (Python/Perl). Degree with significant related experience required (varies by degree).
System Verilog, UVM, VCS, Incisive, Python, Perl
4w
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Hardware Verification Engineer — Electro-Optic Links
Boston or Mountain View
$195k-$250k/yr HybridFull Time
8+ YOE8+ years experience leading verification of high-speed electro-optic/serial links; hands-on lab characterization; expertise with SerDes, signal integrity, and automation using Python/MATLAB.
Python, MATLAB, VNA, BERTs, TDRs, ADS, HFSS, Cadence, COMSOL
3w
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Senior Memory Controller Verification Engineer
Santa Clara or Westford or Austin or Hillsboro or Seattle
$168k-$311k/yr HybridFull Time
6+ YOE6+ years ASIC verification experience, BS/MS or equivalent, SystemVerilog/UVM experience, familiarity with VCS/Debussy/GDB, C/C++ and scripting (Python/Perl/shell), strong debugging and teamwork skills.
VCS, Debussy, GDB, System Verilog, UVM, C, C++, Python, Perl, Shell
3mo
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Design Verification Test (DVT) Manager
Derry, New Hampshire, United States
$125k-$140k/yr OnsiteFull Time
5+ YOE3+ MgmtBachelor's in engineering; 5 years product validation/certification; 3+ years management in test/verification; knowledge of safety design/test; experience with certifications (UL) and ISO; create test processes/reports; support factory releases.
1mo
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Principal Engineer Pre-Silicon Digital Verification
Andover or Austin or El Segundo
$146k-$201k/yr OnsiteFull Time
Expertise in ASIC design and digital/mixed-signal verification, System Verilog and UVM, scripting (Unix/Linux shell, Perl, Python), testbench and coverage development, formal verification and analog behavioral modeling.
System Verilog, UVM, Unix/Linux shell, Perl, Python
3w
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Principal Systems Engineer, Systems Verification Engineer Onsite
Woburn, Massachusetts, United States
$108k-$205k/yr OnsiteFull Time
8+ YOEU.S. citizen with active, transferable Secret security clearance; STEM degree and minimum 8 years relevant experience; experience in systems integration, verification, and test; proficiency with MATLAB, Python, C/C++, Linux/Unix, and Doors.
MATLAB, Python, C/C++, Linux, Unix, Doors
1mo
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Embedded System Verification Engineer - Medical Devices
Westford or Burlington
$69k-$162k/yr OnsiteFull Time
3+ YOEBachelor's degree, 3+ years medical device development experience, verification/testing of embedded hardware systems, knowledge of IEC 60601/62304/ISO 13485/14971, proficiency with Python and LabVIEW, instrumentation experience.
Python, LabVIEW, Oscilloscope, Multimeter, Signal generator
2mo
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Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)
Nashua or Manchester or Largo or New Hampshire or Florida or United States
$130k-$222k/yr OnsiteFull Time
8+ YOEBachelor's degree (or equivalent) with 8+ years experience; ability to obtain Secret clearance; expertise in SystemVerilog/UVM, OVM, VHDL, FPGA/ASIC verification and tools; experience with Mentor Questa or Cadence; strong communication and leadership.
SystemVerilog/UVM, OVM, VHDL, Mentor Questa, Cadence, Perl, Python, C++, Java, Git, Jira, BitBucket, MATLAB, Simulink
1mo
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Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)
San Diego or Nashua or Austin or Totowa or California or New Hampshire or Texas or New Jersey or United States
$130k-$222k/yr OnsiteFull Time
8+ YOEBachelor's degree with 8+ years (or equivalent experience); eligible for Secret clearance; experience with SystemVerilog/UVM/OVM and/or VHDL, Mentor Questa or Cadence tools; FPGA/ASIC verification, test plan development, and strong communication.
SystemVerilog, UVM, OVM, VHDL, Mentor Questa, Cadence, Perl, Python, C++, Java, Git, Jira, BitBucket, Matlab, Simulink
1mo
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Modem HW Design Verification Engineer – AI Driven Next Gen Modem Hardware Development
San Diego or Santa Clara or Boxborough
$128k-$192k/yr OnsiteFull Time
1+ YOEDegree in computer/electrical engineering or related field (BS/MS/PhD) with 1+ years (MS) or 2+ years (BS) engineering experience. Experience in verification planning, SystemVerilog/UVM, RTL languages, C/C++, Python/Perl, Unix/Linux scripting, and GenAI/ML-assisted verification preferred.
SystemVerilog, UVM, OVM, Verilog, VHDL, C, C++, SystemC, Python, Perl, Unix/Linux shell scripting, Makefiles, XML, RTL
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