2,442 verification jobs at 625 companies in California
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Director, Design Verification
San Jose, California, United States
$219k-$351k/yr OnsiteFull Time
15+ YOEBE/MS in Computer/Electrical Engineering or Computer Science; 15+ years ASIC verification; leadership in verification; multiple tape-outs; UVM, C++, SystemVerilog; strong communication and collaborative skills.
UVM, C++, SystemVerilog, verification tools
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Verification Engineer
San Jose or Fort Collins
$120k-$192k/yr OnsiteFull Time
8+ YOEBS in Electrical/Electronic Eng or CS; 8+ years ASIC/RTL verification; SystemVerilog/UVM/OVM; Python/C++; block- and system-level verification; strong debugging and collaboration.
SystemVerilog, UVM, OVM, Python, C/C++, RTL
1mo
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Verification Engineer
San Jose, California, United States
OnsiteFull Time
3+ YOEBS/MS in ECE (or equivalent), 3+ years ASIC/SoC functional verification, strong UVM/SystemVerilog skills, testbench development, scripting in Python/Perl/TCL, and familiarity with regression/CI and hardware-assisted verification.
UVM, SystemVerilog, Python, Perl, TCL, Verilog-AMS, Palladium, Veloce, HAPS, Protium, UPF, UCIe, PCIe, CXL, Ethernet, UALink, VIP
4d
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Design Verification Engineer
Santa Clara or Folsom or Austin
$166k-$250k/yr HybridFull Time
6+ YOEExperienced verification engineer with SystemVerilog, UVM, C/C++, Python or Perl, DDR memory verification, formal verification, and cross-functional hardware, firmware, and software collaboration experience.
SystemVerilog, UVM, C, C++, Python, Perl, DDR5, LPDDR5, LPDDR6, DFI, DIMMs, RTL, BIOS, GLS, NLP, XPROP, VIPs, BFMs
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Design Verification Engineer
Mountain View, California, United States
$120k-$475k/yr HybridFull Time
Concept-to-silicon verification experience; SystemVerilog, Python, C/C++, Bluespec; UVM and assertion-based verification; formal/simulated verification; portable test creation and silicon debug experience.
SystemVerilog, Python, C/C++, Bluespec, UVM, assertion-based verification (ABV)
3w
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Design Verification Manager
Sunnyvale, California, United States
$174k-$353k/yr OnsiteFull Time
10+ YOE5+ Mgmt10+ years pre-silicon ASIC/SoC verification experience, 5+ years engineering management, expert SystemVerilog and UVM, formal verification, emulation platforms, SoC verification strategy and leadership.
SystemVerilog, Universal Verification Methodology (UVM), Palladium, Zebu, Veloce, Artificial Intelligence, Machine Learning, PCIe, CXL, HBM3, NVLink
1mo
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Design Verification Engineer
Mountain View, California, United States
$120k-$475k/yr HybridFull Time
Concept-to-silicon verification experience with SystemVerilog, UVM, ABV, and scripting; production verification and silicon bring-up experience preferred.
SystemVerilog, Python, C/C++, Bluespec, UVM, assertion-based verification (ABV)
2mo
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SoC Verification Lead
Santa Clara, California, United States
$232k-$368k/yr OnsiteFull Time
15+ YOE15+ years of ASIC/SoC functional verification experience; Bachelor's/Master's in EE/CE or equivalent; proficiency in SystemVerilog, UVM, C/C++; experience leading verification to tape-out and managing verification plans, schedules, and risk.
SystemVerilog, UVM, C, C++, EDA
2w
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Senior Verification Engineer
Mountain View, California, United States
$120k-$235k/yr HybridFull Time
5+ YOEAdvanced degree or equivalent experience in EE/CE/CS with multi-year design verification experience; ability to pass cloud background and export-control screenings.
Universal Verification Methodology (UVM), Verilog, Zsh, Bash, Python, Perl, Advanced Microcontroller Bus Architecture (AMBA), AXI-4
3w
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Staff Verification Engineer
Sunnyvale, California, United States
$179k-$219k/yr HybridFull Time
8+ YOE8+ years verification/software experience, strong Ruby/Python skills, deep Linux and networking knowledge, experience with ASIC drivers, mentorship and code-review experience.
Ruby, Python, C, Linux, Docker, Kubernetes, Viavi (Spirent TestCenter, Avalanche), Keysight (Ixia, Breaking Point), Wireshark, CI/CD
1w
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Design Verification Engineer
Santa Clara, California, United States
$45k-$121k/yr OnsiteFull Time
3+ YOERequires 3–5 years of experience with VLSI hardware verification, SystemVerilog, UVM, AMBA protocols, test planning, coverage analysis, simulation debugging, regressions, and power-aware verification.
SystemVerilog, UVM, AMBA, UPF, CPF, VLSI, HVL
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Design Verification Engineer
San Francisco, California, United States
OnsiteFull Time
Digital-focused design verification for pre-silicon IP: DV methodology, test-plan and verification environment development, test writing, debug, coverage, and RTL sign-off for tape-out.
2mo
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Formal Verification Engineer
San Jose, California, United States
$150k-$350k/yr OnsiteFull Time
Deep formal verification expertise, experience with assertion-based verification and proof debugging, proficiency scripting in Python or Tcl, and hands-on use of formal EDA tools to verify RTL and production IP.
JasperGold, VC Formal, Questa Formal, SystemVerilog Assertions (SVA), Python, Tcl
3mo
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ASIC verification engineer
Roseville, California, United States
$120k-$243k/yr OnsiteFull Time
6+ YOEBachelor's or Master's in Electrical/Computer Engineering; 6-10 years VLSI design/verification; Verilog/SystemVerilog/UVM; scripting (Python/Perl/TCL); C/C++; EDA/verification tools.
Verilog, SystemVerilog, UVM, Specman, Python, Perl, TCL, C, C++, EDA tools
3w
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Design Verification Engineer
Aliso Viejo or San Jose or Córdoba or Toronto
OnsiteFull Time
3+ YOEBachelors in EE/CE/CS,3+ years verification experience, SystemVerilog/UVM, coverage-driven verification, C/C++ and scripting (Python,Tcl,Perl),test planning and debug skills.
SystemVerilog, UVM, C, C++, Python, Tcl, Perl
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Principal Verification Engineer
Austin or Santa Clara
OnsiteFull Time
12+ YOE+12 years of experience; BS or MS in Computer Science, Electrical Engineering, or related field; experience with microarchitecture, CPU design, verification flow; strong analytical and troubleshooting skills; ability to collaborate across teams.
3w
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Design Verification Manager
Sunnyvale, California, United States
$174k-$353k/yr OnsiteFull Time
10+ YOE5+ Mgmt10+ years pre-silicon ASIC/SoC verification experience, 5+ years engineering management, expert SystemVerilog/UVM, formal verification, emulation experience, BS in EE/CS/CE or related.
SystemVerilog, Universal Verification Methodology (UVM), Palladium, Zebu, Veloce
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Senior Verification Engineer
Santa Clara, California, United States
$168k-$311k/yr HybridFull Time
10+ YOE10+ years verification experience, strong UVM/SystemVerilog/Verilog/Python/C/C++ skills, experience with constrained-random stimulus, coverage, assertions, and EDA tools; BS/MS in EE/CE/CS or equivalent experience.
UVM, SystemVerilog, Verilog, Python, C/C++, VCS, Verdi, Debussy, GDB, HLS
2mo
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Formal Verification - DV
San Jose, California, United States
OnsiteFull Time
5+ YOE5+ years design verification with hands-on formal verification experience; strong SystemVerilog/SVA skills; experience with commercial formal tools; deep digital design and SoC interface knowledge; strong RTL/debug skills.
SystemVerilog, SystemVerilog Assertions, UVM, Cadence JasperGold, Synopsys VC Formal, Siemens Questa Formal, Python, TCL, Perl
3mo
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Design Verification Architect
San Jose or United States
$150k-$300k/yr HybridFull Time
12+ YOEBachelor's/Master's in EE/CE, 12+ years design verification experience for large SoCs, expertise in SystemVerilog, UVM, Portable Stimulus (PSS), coverage-driven and assertion-based verification, and strong architecture and debugging skills.
SystemVerilog, UVM, Portable Stimulus (PSS), PCIe, DDR, Ethernet, CXL, UCIe
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