180 verification engineer jobs at 71 companies in Concord, MA
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Senior Verification Engineer
Wilmington, Massachusetts, United States
$110k-$152k/yr OnsiteFull Time
4+ YOE4+ years verification experience with SystemVerilog/UVM, RTL simulation and debug, scripting (Python/Perl/Tcl), SoC/processor verification, and strong analytical/debugging skills.
SystemVerilog, UVM, VCS, Xcelium, Simvision, Verdi, Questa, Python, Perl, Tcl, Linux, ARM Cortex-M, RISC-V, APB, AHB, AXI, QSPI, UART, DMA
1w
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Formal Verification Engineer
Austin or Boston or Santa Clara
$127k-$217k/yr HybridFull Time
8+ YOERequires 8+ years in design verification focused on formal verification, VC Formal or JasperGold, SystemVerilog Assertions, TCL/Python/Perl, and a bachelor's or master's degree in computer or electrical engineering.
VC Formal, JasperGold, SystemVerilog Assertions (SVA), TCL, Python, Perl
6d
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FPGA Verification Engineer
Waltham, Massachusetts, United States
$166k-$220k/yr OnsiteFull Time
8+ YOEBachelor's in electrical engineering, computer engineering, or related technical field; 8+ years developing FPGA HDL firmware; VHDL/Verilog, SystemVerilog, verification testbenches, Git or Subversion, and Secret clearance eligibility.
SystemVerilog, OVM, UVM, VHDL, Verilog, Git, Subversion, Unix, Linux, C, C++, Python, Perl, QuestaSim, Synplify, Quartus, Vivado
4d
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Verification Engineer - New College Grad 2026
Santa Clara or Westford or Austin
$100k-$190k/yr OnsiteFull Time
Bachelor's or master's degree in electrical or computer engineering, C++ and SystemVerilog experience, scripting, verification methodologies, testbench architecture, debugging, and analytical and communication skills.
C++, SystemVerilog, VCS, Debussy, GDB
4d
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Verification Engineer - New College Grad 2026
Santa Clara or Austin or Westford
$100k-$190k/yr OnsiteFull Time
Bachelor's or master's degree in electrical or computer engineering, testbench and verification experience, C++ programming, scripting, SystemVerilog, simulation and debugging tools, and strong analytical skills.
C++, SystemVerilog, VCS, Debussy, GDB
2mo
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Design Verification Engineer - Viasat Government
Marlborough or Carlsbad
$133k-$210k/yr OnsiteFull Time
5+ YOEBachelor's in Electrical or Computer Engineering; 5+ years hardware verification with SystemVerilog/UVM; RTL verification; strong SystemVerilog/UVM; experience with industry EDA tools; US citizenship and active Secret clearance; willingness to travel up to 10%
SystemVerilog, UVM, Siemens Questa, Cadence, Synopsys, Mentor, Python, TCL
2mo
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Senior Principal Engineer, Design Verification
Westborough, Massachusetts, United States
$205k-$303k/yr OnsiteFull Time
10+ YOEDegree in electrical/computer engineering, 10+ years verification experience (block-to-chip), strong System Verilog/UVM, Python or Perl, EDA tools, testplan/coverage development, technical leadership and debugging skills.
System Verilog, UVM, Python, Perl, EDA verification tools
2mo
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Design Verification Engineer - Viasat Government
Marlborough or Carlsbad
$133k-$210k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE or related,5+ years hardware verification experience with SystemVerilog/UVM,experience with industry EDA tools,US citizenship and active Secret clearance required,ability to travel up to 10%.
SystemVerilog, UVM, Siemens Questa, Cadence, Synopsys, Mentor, AMD/Xilinx Vivado, Altera Quartus, Microchip Libero, TCL, Perl, Python, Linux
2mo
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ASIC Design Verification Engineer
Irvine or Andover or Broomfield
$129k-$207k/yr OnsiteFull Time
3+ YOEConstrained-random design verification experience using System Verilog/UVM, coverage-driven methodologies, experience with VCS/Incisive and scripting (Python/Perl). Degree with significant related experience required (varies by degree).
System Verilog, UVM, VCS, Incisive, Python, Perl
1w
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Design Verification Engineer
Waltham, Massachusetts, United States
OnsiteFull Time
Responsible for verifying the functionality and performance of Apple's system-on-chip products; the posting does not specify education, certifications, or experience requirements.
3mo
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Staff Design Verification Engineer – Coherent Interconnect
Boston or Austin
OnsiteFull Time
7+ YOELead verification for cache-coherent interconnect; 7+ years ASIC/SoC verification; SystemVerilog/UVM expertise; strong debugging and collaboration skills.
SystemVerilog, UVM, Verilog, Python
1mo
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Principal Systems Engineer, Systems Verification Engineer Onsite
Woburn, Massachusetts, United States
$108k-$205k/yr OnsiteFull Time
8+ YOEU.S. citizen with active, transferable Secret security clearance; STEM degree and minimum 8 years relevant experience; experience in systems integration, verification, and test; proficiency with MATLAB, Python, C/C++, Linux/Unix, and Doors.
MATLAB, Python, C/C++, Linux, Unix, Doors
1mo
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Hardware Verification Engineer — Electro-Optic Links
Boston or Mountain View
$195k-$250k/yr HybridFull Time
8+ YOE8+ years experience leading verification of high-speed electro-optic/serial links; hands-on lab characterization; expertise with SerDes, signal integrity, and automation using Python/MATLAB.
Python, MATLAB, VNA, BERTs, TDRs, ADS, HFSS, Cadence, COMSOL
1mo
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Verification & Validation Test Engineer
Manchester, New Hampshire, United States
OnsiteFull Time
3+ YOEBS in engineering, 3+ years testing electro-mechanical devices, lab and fluid-handling skills, mentorship experience, strong written/verbal communication, and problem-solving skills.
3d
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Senior Software Verification Engineer
Burlington, Massachusetts, United States
$78k-$156k/yr OnsiteFull Time
5+ YOERequires 5+ years of regulated medical-device software verification experience, IEC 62304 and FDA design-control knowledge, strong communication, and onsite hardware-testing availability.
Squish, Appium, XCUITest, Espresso, Python, Java, C, C++, iOS, Android, BLE, Wi-Fi, Cellular, NFC
2mo
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Modem HW Design Verification Engineer – AI Driven Next Gen Modem Hardware Development
San Diego or Santa Clara or Boxborough
$128k-$192k/yr OnsiteFull Time
1+ YOEDegree in computer/electrical engineering or related field (BS/MS/PhD) with 1+ years (MS) or 2+ years (BS) engineering experience. Experience in verification planning, SystemVerilog/UVM, RTL languages, C/C++, Python/Perl, Unix/Linux scripting, and GenAI/ML-assisted verification preferred.
SystemVerilog, UVM, OVM, Verilog, VHDL, C, C++, SystemC, Python, Perl, Unix/Linux shell scripting, Makefiles, XML, RTL
3d
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Senior Software Verification Engineer
Burlington, Massachusetts, United States
$78k-$156k/yr OnsiteFull Time
5+ YOERequires 5+ years of software verification experience in medical devices or regulated industries, IEC 62304 and FDA design control knowledge, and strong communication skills. Python and mobile or embedded testing experience preferred.
Squish, Appium, XCUITest, Espresso, Python, Java, C, C++, iOS, Android, BLE, Wi-Fi, Cellular, NFC, IEC 62304, ISO 13485, FDA
2mo
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Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)
Nashua or Manchester or Largo or New Hampshire or Florida or United States
$130k-$222k/yr OnsiteFull Time
8+ YOEBachelor's degree (or equivalent) with 8+ years experience; ability to obtain Secret clearance; expertise in SystemVerilog/UVM, OVM, VHDL, FPGA/ASIC verification and tools; experience with Mentor Questa or Cadence; strong communication and leadership.
SystemVerilog/UVM, OVM, VHDL, Mentor Questa, Cadence, Perl, Python, C++, Java, Git, Jira, BitBucket, MATLAB, Simulink
1mo
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Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)
San Diego or Nashua or Austin or Totowa or California or New Hampshire or Texas or New Jersey or United States
$130k-$222k/yr OnsiteFull Time
8+ YOEBachelor's degree with 8+ years (or equivalent experience); eligible for Secret clearance; experience with SystemVerilog/UVM/OVM and/or VHDL, Mentor Questa or Cadence tools; FPGA/ASIC verification, test plan development, and strong communication.
SystemVerilog, UVM, OVM, VHDL, Mentor Questa, Cadence, Perl, Python, C++, Java, Git, Jira, BitBucket, Matlab, Simulink
1mo
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Design Verification Engineer – Physical AI Compute
Santa Clara or Austin or Boston
$75k-$275k/yr OnsiteFull Time
Experience verifying complex digital/SoC systems with SystemVerilog/UVM, C/C++, assertions, formal, emulation and debugging across HW/SW boundaries.
SystemVerilog, UVM, C, C++, formal verification, emulation, FPGA
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