157 verification engineer jobs at 67 companies in Epping, NH
1w
Save
Mark Applied
Hide
Senior Verification Engineer
Wilmington, Massachusetts, United States
$110k-$152k/yr OnsiteFull Time
4+ YOE4+ years verification experience with SystemVerilog/UVM, RTL simulation and debug, scripting (Python/Perl/Tcl), SoC/processor verification, and strong analytical/debugging skills.
SystemVerilog, UVM, VCS, Xcelium, Simvision, Verdi, Questa, Python, Perl, Tcl, Linux, ARM Cortex-M, RISC-V, APB, AHB, AXI, QSPI, UART, DMA
2w
Save
Mark Applied
Hide
Formal Verification Engineer
Boxborough or Austin or Boston or Santa Clara
HybridFull Time
8+ YOE8+ years design verification experience with strong focus on formal verification, proficiency with VC Formal/JasperGold, SVA, formal methods, and scripting (TCL, Python, Perl); Bachelors/Masters in CE/EE.
VC Formal, JasperGold, SystemVerilog Assertions (SVA), TCL, Python, Perl
2mo
Save
Mark Applied
Hide
Senior Formal Verification Engineer
Santa Clara or Austin or Westford or Hillsboro
$168k-$311k/yr HybridFull Time
7+ YOE7+ years experience with formal verification, strong knowledge of Verilog/System Verilog, temporal logic assertions, abstraction techniques, scripting in TCL/Perl/Python, and solid understanding of CPU/GPU architectures.
Verilog, System Verilog, temporal logic assertions, TCL, Perl, Python, Jasper Gold, VC Formal, RTL
1mo
Save
Mark Applied
Hide
ASIC Design Verification Engineer
Irvine or Andover or Broomfield
$129k-$207k/yr OnsiteFull Time
3+ YOEConstrained-random design verification experience using System Verilog/UVM, coverage-driven methodologies, experience with VCS/Incisive and scripting (Python/Perl). Degree with significant related experience required (varies by degree).
System Verilog, UVM, VCS, Incisive, Python, Perl
2mo
Save
Mark Applied
Hide
ASIC/FPGA Verification Engineer IV
Denver or Highlands Ranch or Sunnyvale or Cambridge
$124k-$246k/yr OnsiteFull Time
5+ YOEBachelors in EE (or equivalent), 5+ years FPGA/ASIC verification experience, UVM/SystemVerilog/VHDL/Verilog expertise, experience with modern verification methodologies and tools, and ability to obtain DoD Secret clearance (US citizenship required).
SystemVerilog, Universal Verification Methodology (UVM), VHDL, Verilog, Linux, Microsoft Project, JIRA, Python, OVM, VMM
2mo
Save
Mark Applied
Hide
Staff Design Verification Engineer – Coherent Interconnect
Boston or Austin
OnsiteFull Time
7+ YOELead verification for cache-coherent interconnect; 7+ years ASIC/SoC verification; SystemVerilog/UVM expertise; strong debugging and collaboration skills.
SystemVerilog, UVM, Verilog, Python
3w
Save
Mark Applied
Hide
Principal Systems Engineer, Systems Verification Engineer Onsite
Woburn, Massachusetts, United States
$108k-$205k/yr OnsiteFull Time
8+ YOEU.S. citizen with active, transferable Secret security clearance; STEM degree and minimum 8 years relevant experience; experience in systems integration, verification, and test; proficiency with MATLAB, Python, C/C++, Linux/Unix, and Doors.
MATLAB, Python, C/C++, Linux, Unix, Doors
1mo
Save
Mark Applied
Hide
Hardware Verification Engineer — Electro-Optic Links
Boston or Mountain View
$195k-$250k/yr HybridFull Time
8+ YOE8+ years experience leading verification of high-speed electro-optic/serial links; hands-on lab characterization; expertise with SerDes, signal integrity, and automation using Python/MATLAB.
Python, MATLAB, VNA, BERTs, TDRs, ADS, HFSS, Cadence, COMSOL
1mo
Save
Mark Applied
Hide
Senior Memory Controller Verification Engineer
Santa Clara or Westford or Austin or Hillsboro or Seattle
$168k-$311k/yr HybridFull Time
6+ YOE6+ years ASIC verification experience, BS/MS or equivalent, SystemVerilog/UVM experience, familiarity with VCS/Debussy/GDB, C/C++ and scripting (Python/Perl/shell), strong debugging and teamwork skills.
VCS, Debussy, GDB, System Verilog, UVM, C, C++, Python, Perl, Shell
2w
Save
Mark Applied
Hide
Verification & Validation Test Engineer
Manchester, New Hampshire, United States
OnsiteFull Time
3+ YOEBS in engineering, 3+ years testing electro-mechanical devices, lab and fluid-handling skills, mentorship experience, strong written/verbal communication, and problem-solving skills.
2mo
Save
Mark Applied
Hide
Modem HW Design Verification Engineer – AI Driven Next Gen Modem Hardware Development
San Diego or Santa Clara or Boxborough
$128k-$192k/yr OnsiteFull Time
1+ YOEDegree in computer/electrical engineering or related field (BS/MS/PhD) with 1+ years (MS) or 2+ years (BS) engineering experience. Experience in verification planning, SystemVerilog/UVM, RTL languages, C/C++, Python/Perl, Unix/Linux scripting, and GenAI/ML-assisted verification preferred.
SystemVerilog, UVM, OVM, Verilog, VHDL, C, C++, SystemC, Python, Perl, Unix/Linux shell scripting, Makefiles, XML, RTL
3mo
Save
Mark Applied
Hide
CPU Design Verification Engineer
Cambridge or Boston
OnsiteFull Time
3+ YOEBS plus 3+ years in CPU architecture/digital logic; experience with test plans/testbenches; languages C, C++, or SystemVerilog.
SystemVerilog, C, C++, assembly, testbenches
2mo
Save
Mark Applied
Hide
Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)
Nashua or Manchester or Largo or New Hampshire or Florida or United States
$130k-$222k/yr OnsiteFull Time
8+ YOEBachelor's degree (or equivalent) with 8+ years experience; ability to obtain Secret clearance; expertise in SystemVerilog/UVM, OVM, VHDL, FPGA/ASIC verification and tools; experience with Mentor Questa or Cadence; strong communication and leadership.
SystemVerilog/UVM, OVM, VHDL, Mentor Questa, Cadence, Perl, Python, C++, Java, Git, Jira, BitBucket, MATLAB, Simulink
1mo
Save
Mark Applied
Hide
Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)
San Diego or Nashua or Austin or Totowa or California or New Hampshire or Texas or New Jersey or United States
$130k-$222k/yr OnsiteFull Time
8+ YOEBachelor's degree with 8+ years (or equivalent experience); eligible for Secret clearance; experience with SystemVerilog/UVM/OVM and/or VHDL, Mentor Questa or Cadence tools; FPGA/ASIC verification, test plan development, and strong communication.
SystemVerilog, UVM, OVM, VHDL, Mentor Questa, Cadence, Perl, Python, C++, Java, Git, Jira, BitBucket, Matlab, Simulink
1mo
Save
Mark Applied
Hide
Design Verification Engineer, PLM
Portsmouth, New Hampshire, United States
OnsiteFull Time
2+ YOEBachelor's in engineering and 2+ years experience in design, development, and testing; knowledge of design control, validation, and regulatory standards; proficiency with test documentation and engineering change processes.
Azure DevOps, JIRA, Greenlight Guru, SAP
3w
Save
Mark Applied
Hide
Design Verification Engineer – Physical AI Compute
Santa Clara or Austin or Boston
$75k-$275k/yr OnsiteFull Time
Experience verifying complex digital/SoC systems with SystemVerilog/UVM, C/C++, assertions, formal, emulation and debugging across HW/SW boundaries.
SystemVerilog, UVM, C, C++, formal verification, emulation, FPGA
2mo
Save
Mark Applied
Hide
Member of Technical Staff, Formal Verification
Santa Clara or Boston
OnsiteFull Time
10+ YOEBachelor's or Master's in EE/CE, 10+ years ASIC/SoC verification with 7+ years formal verification, expertise in SVA and formal tools, scripting (Tcl/Python/Perl/Shell), strong debugging and leadership skills.
SystemVerilog Assertions (SVA), Cadence JasperGold, Synopsys VC Formal, Siemens Questa Formal, UVM, Tcl, Python, Perl, Shell
5d
Save
Mark Applied
Hide
Hardware Verification Engineer (Defense & Aerospace, North Reading, MA)
North Reading, Massachusetts, United States
$67k-$108k/yr OnsiteFull Time
1+ YOEBachelor's degree in Electrical or Computer Engineering, 1–3 years of relevant experience, C/C++/C# and .NET knowledge, test equipment experience, circuit theory, signal tracing, teamwork, and communication skills.
C, C++, C#, .NET, oscilloscopes, DMMs, waveform generators, PC
1w
Save
Mark Applied
Hide
Senior System Engineer - Integration & Verification
Boston, Massachusetts, United States
$165k-$195k/yr HybridFull Time
6+ YOEBS in engineering required (MS preferred),6+ years I&V/systems engineering experience with flight control systems, requirements management, test plan/procedure development, and cross-functional collaboration.
Simulink, Cameo, IADS, Jama, Model-based Systems Engineering (MBSE), ARP4754A, RTCA DO-178B/C
3mo
Save
Mark Applied
Hide
Design Verification Test (DVT) Manager
Derry, New Hampshire, United States
$125k-$140k/yr OnsiteFull Time
5+ YOE3+ MgmtBachelor's in engineering; 5 years product validation/certification; 3+ years management in test/verification; knowledge of safety design/test; experience with certifications (UL) and ISO; create test processes/reports; support factory releases.
Explore Jobs