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Senior Verification Engineer
Wilmington, Massachusetts, United States
$110k-$152k/yr OnsiteFull Time
4+ YOE4+ years verification experience with SystemVerilog/UVM, RTL simulation and debug, scripting (Python/Perl/Tcl), SoC/processor verification, and strong analytical/debugging skills.
SystemVerilog, UVM, VCS, Xcelium, Simvision, Verdi, Questa, Python, Perl, Tcl, Linux, ARM Cortex-M, RISC-V, APB, AHB, AXI, QSPI, UART, DMA
3mo
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Design Verification Engineer
Waltham, Massachusetts, United States
OnsiteFull Time
10+ YOEBS or higher with 10+ years in digital verification; strong SystemVerilog, verification methodologies (UVM), Python/Perl; hardware/SOC DV experience.
SystemVerilog, Python, Perl, C++, C, UVM, Debugging, Digital Verification
1w
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Formal Verification Engineer
Boxborough or Austin or Boston or Santa Clara
HybridFull Time
8+ YOE8+ years design verification experience with strong focus on formal verification, proficiency with VC Formal/JasperGold, SVA, formal methods, and scripting (TCL, Python, Perl); Bachelors/Masters in CE/EE.
VC Formal, JasperGold, SystemVerilog Assertions (SVA), TCL, Python, Perl
3mo
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GPU Verification Engineer
Westford, Massachusetts, United States
OnsiteFull Time
2+ YOEBachelor's in Electrical/Computer Engineering or Computer Science; 5+ years experience or 2+ years with Bachelor's; proficient in C/C++, scripting; strong debugging and problem solving; knowledge of computer architecture; exposure to verification tools; good communication.
C/C++, Perl, Python, Shell, VCS, Emulation, FPGA
2mo
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Design Verification Engineer - Viasat Government
Marlborough or Carlsbad
$133k-$210k/yr OnsiteFull Time
5+ YOEBachelor's in Electrical or Computer Engineering; 5+ years hardware verification with SystemVerilog/UVM; RTL verification; strong SystemVerilog/UVM; experience with industry EDA tools; US citizenship and active Secret clearance; willingness to travel up to 10%
SystemVerilog, UVM, Siemens Questa, Cadence, Synopsys, Mentor, Python, TCL
3mo
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Principal Design Verification Engineer
Morrisville or Westborough
$160k-$237k/yr OnsiteFull Time
10+ YOEVerify SoC design with SystemVerilog/UVM; develop verification environment; write tests; debug issues; strong scripting.
SystemVerilog, UVM, Python, Perl, C++, EDA tools, ARM
1mo
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ASIC Design Verification Engineer
Irvine or Andover or Broomfield
$129k-$207k/yr OnsiteFull Time
3+ YOEConstrained-random design verification experience using System Verilog/UVM, coverage-driven methodologies, experience with VCS/Incisive and scripting (Python/Perl). Degree with significant related experience required (varies by degree).
System Verilog, UVM, VCS, Incisive, Python, Perl
2mo
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ASIC/FPGA Verification Engineer IV
Denver or Highlands Ranch or Sunnyvale or Cambridge
$124k-$246k/yr OnsiteFull Time
5+ YOEBachelors in EE (or equivalent), 5+ years FPGA/ASIC verification experience, UVM/SystemVerilog/VHDL/Verilog expertise, experience with modern verification methodologies and tools, and ability to obtain DoD Secret clearance (US citizenship required).
SystemVerilog, Universal Verification Methodology (UVM), VHDL, Verilog, Linux, Microsoft Project, JIRA, Python, OVM, VMM
3mo
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Principal Electrical Engineer-FPGA Verification
Tewksbury or Marlborough
$108k-$205k/yr OnsiteFull Time
8+ YOE8+ years in digital design verification; SystemVerilog; UVM; FPGA verification; DoD/DoD-style security clearance.
SystemVerilog, UVM, AXI, PCIe, Ethernet, DDR, Questa, VCS, Xcelium, Git, ClearCase, SVN, Vivado, Quartus, Python, Tcl, Perl, VHDL, SLURM
2mo
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Staff Design Verification Engineer – Coherent Interconnect
Boston or Austin
OnsiteFull Time
7+ YOELead verification for cache-coherent interconnect; 7+ years ASIC/SoC verification; SystemVerilog/UVM expertise; strong debugging and collaboration skills.
SystemVerilog, UVM, Verilog, Python
3w
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Hardware Verification Engineer — Electro-Optic Links
Boston or Mountain View
$195k-$250k/yr HybridFull Time
8+ YOE8+ years experience leading verification of high-speed electro-optic/serial links; hands-on lab characterization; expertise with SerDes, signal integrity, and automation using Python/MATLAB.
Python, MATLAB, VNA, BERTs, TDRs, ADS, HFSS, Cadence, COMSOL
1w
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Verification & Validation Test Engineer
Manchester, New Hampshire, United States
OnsiteFull Time
3+ YOEBS in engineering, 3+ years testing electro-mechanical devices, lab and fluid-handling skills, mentorship experience, strong written/verbal communication, and problem-solving skills.
4w
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Embedded System Verification Engineer - Medical Devices
Westford or Burlington
$69k-$162k/yr OnsiteFull Time
3+ YOEBachelor's degree, 3+ years medical device development experience, verification/testing of embedded hardware systems, knowledge of IEC 60601/62304/ISO 13485/14971, proficiency with Python and LabVIEW, instrumentation experience.
Python, LabVIEW, Oscilloscope, Multimeter, Signal generator
2mo
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Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)
Nashua or Manchester or Largo or New Hampshire or Florida or United States
$130k-$222k/yr OnsiteFull Time
8+ YOEBachelor's degree (or equivalent) with 8+ years experience; ability to obtain Secret clearance; expertise in SystemVerilog/UVM, OVM, VHDL, FPGA/ASIC verification and tools; experience with Mentor Questa or Cadence; strong communication and leadership.
SystemVerilog/UVM, OVM, VHDL, Mentor Questa, Cadence, Perl, Python, C++, Java, Git, Jira, BitBucket, MATLAB, Simulink
1mo
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Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)
San Diego or Nashua or Austin or Totowa or California or New Hampshire or Texas or New Jersey or United States
$130k-$222k/yr OnsiteFull Time
8+ YOEBachelor's degree with 8+ years (or equivalent experience); eligible for Secret clearance; experience with SystemVerilog/UVM/OVM and/or VHDL, Mentor Questa or Cadence tools; FPGA/ASIC verification, test plan development, and strong communication.
SystemVerilog, UVM, OVM, VHDL, Mentor Questa, Cadence, Perl, Python, C++, Java, Git, Jira, BitBucket, Matlab, Simulink
1mo
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Design Verification Engineer, PLM
Portsmouth, New Hampshire, United States
OnsiteFull Time
2+ YOEBachelor's in engineering and 2+ years experience in design, development, and testing; knowledge of design control, validation, and regulatory standards; proficiency with test documentation and engineering change processes.
Azure DevOps, JIRA, Greenlight Guru, SAP
1mo
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Design Verification & Test Development Engineer
Bedford, Massachusetts, United States
$64k-$92k/yr OnsiteFull Time
3+ YOE3+ years developing and executing test methods for electromechanical products; BS in Engineering; Python and data analysis (Pandas, NumPy, Matplotlib); experience with test equipment (LabVIEW, PLC, Raspberry Pi, HALT/thermal/vibration chambers); strong communication and problem solving.
Python, Pandas, NumPy, Matplotlib, PLC, Raspberry Pi, LabVIEW, C#, HALT chambers, thermal chambers, vibration tables, power analyzers, pneumatics, oscilloscopes, multi-meters, AI
1mo
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Member of Technical Staff, Formal Verification
Santa Clara or Boston
OnsiteFull Time
10+ YOEBachelor's or Master's in EE/CE, 10+ years ASIC/SoC verification with 7+ years formal verification, expertise in SVA and formal tools, scripting (Tcl/Python/Perl/Shell), strong debugging and leadership skills.
SystemVerilog Assertions (SVA), Cadence JasperGold, Synopsys VC Formal, Siemens Questa Formal, UVM, Tcl, Python, Perl, Shell
1mo
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Embedded Software Verification Engineer – Surgical Robotics (Cambridge, MA)
Cambridge, Massachusetts, United States
$114k-$182k/yr OnsiteFull Time
3+ YOE3+ years verifying embedded real-time software; Bachelor's degree in CS/Software Engineering/IT; strong C++, RTOS, embedded Linux, Python, hardware-in-the-loop testing; experience in regulated/safety-critical environments preferred.
C++, RTOS, embedded Linux, Python
1mo
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Principal Engineer Pre-Silicon Digital Verification
Andover or Austin or El Segundo
$146k-$201k/yr OnsiteFull Time
Expertise in ASIC design and digital/mixed-signal verification, System Verilog and UVM, scripting (Unix/Linux shell, Perl, Python), testbench and coverage development, formal verification and analog behavioral modeling.
System Verilog, UVM, Unix/Linux shell, Perl, Python
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