3mo
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PMU Design Verification Engineer: Analog & Mixed Signal Engineer
Austin or Cupertino
OnsiteFull Time
3+ YOEBS and 3+ years in analog/mixed-signal verification; strong Verilog/System-Verilog/Verilog-AMS; test plans, simulations, and cross-functional collaboration.
Verilog, SystemVerilog, Verilog-AMS, TCL, Python, Perl
1w
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MTS Logic Design
Hillsboro, Oregon, United States
$86k-$160k/yr HybridFull Time
Bachelor's degree in engineering, knowledge of Verilog/System Verilog, RTL design and verification, strong communication skills.
Verilog, System Verilog, RTL
1mo
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Staff Design Engineer - HBM Design
Richardson, Texas, United States
OnsiteFull Time
5+ YOEBachelor's in EE/Electronics + 5 years experience. CMOS and high-speed circuit design, HBM design/verification, System Verilog/Verilog/UVM, layout extraction, Verilog-SPICE co-sim, and scripting (Python/Tcl).
FINESIM, HSPICE, VERILOG, System Verilog, UVM, Python, Tcl, SPF, SDF
1mo
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Senior ASIC Verification Engineer
Austin, Texas, United States
$136k-$265k/yr OnsiteFull Time
3+ YOE3+ years relevant experience, Bachelor's/Master's in Computer or Electrical Engineering (or equivalent), proficiency in System Verilog, UVM, Python, Verilog, RTL, and familiarity with VCS and Verdi.
System Verilog, UVM, Python, Verilog, RTL, VCS, Verdi
2mo
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Design Engineer Verification (2026 New College Graduate)
Richardson, Texas, United States
$72k-$148k/yr OnsiteFull Time
Bachelor's or Master's in Electrical/Electronics/Computer Engineering, 3.0+ GPA, knowledge of Verilog/System-Verilog, RISC V architecture, UNIX and assembly, strong communication and documentation skills.
Verilog, System-Verilog, RISCV, UNIX, Assembly
4d
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AE - Verification IP
San Jose or Austin
$84k-$156k/yr OnsiteFull Time
2+ YOEExpertise in PCIe and AMBA protocols, 2+ years design verification experience, Verilog/System Verilog/UVM skills, degree in electrical/computer engineering, debugging and communication skills.
Verilog, System Verilog, UVM, waveform viewers, simulation analysis tools
4d
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Senior FPGA Engineer
Beaverton, Oregon, United States
HybridFull Time
5+ YOEBachelor's in EE/CE required, 5+ years FPGA design experience, Verilog/System Verilog, FPGA device architecture, verification (UVM) and strong analytic and communication skills.
Verilog, System Verilog, Intel FPGA, Xilinx FPGA, UVM, C, C++, TCL, Python
4d
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Senior Silicon Engineer
Redmond or Mountain View or Santa Clara or Austin or Raleigh or Hillsboro or Boise
$120k-$235k/yr HybridFull Time
5+ YOEExperience verifying silicon using UVM/C, strong RTL and SoC verification background, proficiency with Verilog/System Verilog, and relevant EE/CS/CE degree or equivalent experience.
UVM, C, Verilog, System Verilog, Microsoft Excel
3mo
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Engineer Principal - FPGA Design - $15K Sign-On Bonus
Westminster, Colorado, United States
$118k-$201k/yr HybridFull Time
6+ YOEBS in Engineering (or equivalent) plus 6+ years experience; expertise in FPGA design, VHDL/Verilog/System Verilog, Xilinx Vivado/Vitis, Mentor Modelsim/Questasim; U.S. person required.
VHDL, Verilog, System Verilog, Xilinx Vivado, Vitis, Mentor Modelsim, Questasim, OVM, UVM, Mentor Graphic Hyperlynx
1w
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Mixed Signal Design Verification Engineer
Hillsboro, Oregon, United States
$142k-$200k/yr HybridFull Time
2+ YOEBachelor's in EE/CE/CS with 3+ years or Master's with 2+ years; digital logic and VHDL/Verilog/System Verilog experience; testbench development (OVM/UVM); strong debug skills.
VHDL, Verilog, System Verilog, OVM, UVM
3d
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Digital Verification Engineer
Santa Clara, California, United States
OnsiteFull Time
3+ YOE3+ years digital verification experience for FPGA/ASIC, proficiency in Verilog/SystemVerilog, experience with Modelsim/Questasim or NC-Verilog, BS/MS in EE/CE, strong coverage and assertion skills.
Verilog, SystemVerilog, Modelsim, Questasim, NC-Verilog, UVM
2mo
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Modem HW Design Engineer – AI Driven Next Gen Modem Hardware Development
San Diego or Santa Clara or Boxborough
$104k-$192k/yr OnsiteFull Time
1+ YOEBachelor's in engineering or related; 1+ year industry/programming experience; RTL/Verilog/System Verilog and modem development experience; familiarity with synthesis, verification, Unix/Linux shell scripting, Python/Perl.
C, C++, Python, Verilog, System Verilog, Unix/Linux shell scripting, Perl, Makefiles, XML
1mo
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THW Client Co-op
Pittsford or New York
$27-$38/hr OnsiteFull Time, Internship
Student in a Bachelor's program in Electrical or Computer Engineering; experience with ASIC/FPGA and System Verilog/Verilog/VHDL/Python preferred; strong verbal and technical writing skills; self-motivated team player.
System Verilog, UVM, Verilog, VHDL, Python, Linux, FPGA, ASIC, Wavelogic
2d
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ASIC DFT Emulation Technical Lead
San Jose, California, United States
$184k-$264k/yr OnsiteFull Time
3+ YOEDesign and lead DFT emulation environments; prior emulation (Palladium/Veloce/Zebu), Verilog/System Verilog, C/C++, scripting (Tcl/Python/Perl), and 6–8+ years experience required.
Palladium, Veloce, Zebu, Verilog, System Verilog, C, C++, Tcl, Python, Perl, UVM
1d
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Principal Engineer - Design
Hauppauge, New York, United States
$75k-$232k/yr OnsiteFull Time
10+ YOEBachelor's in Electrical Engineering or equivalent,10+ years relevant experience,Verilog/System Verilog proficiency,experience with Ethernet/USB/PCIe and ASIC design/verification,strong problem solving and communication skills.
Verilog, System Verilog, Xilinx FPGA
1w
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Sr. Silicon Design Engineer
San Jose or United States
$124k-$213k/yr HybridFull Time
Bachelor's or Master's in EE/CE, strong RTL/Verilog/System Verilog skills, experience with design checker tools, synthesis and static timing, SerDes/PHY knowledge, and scripting with Python/Perl/TCL.
Verilog, System Verilog, Python, Perl, TCL, LINT, CDC, RDC
2mo
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Junior Engineer, FPGA
Princeton, New Jersey, United States
$60k-$62k/yr OnsiteFull Time
FPGA design with Verilog/VHDL or HLS; testbench development; target/retarget FPGA designs; knowledge of Verilog, VHDL, SystemVerilog and C; experience with timing closure and Xilinx boards; document design data sheets.
Verilog, VHDL, SystemVerilog, C, Xilinx tools, FPGA
1w
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CPU Design Methodology Engineer
Hillsboro or Austin or Santa Clara or United States
$136k-$265k/yr HybridFull Time
5+ YOEMasters in Computer/Electrical Engineering or equivalent experience,5+ years chip/SOC design experience,RTL (Verilog),UVM/System Verilog,design automation,Perl/Python skills,analytical and interpersonal skills.
Verilog, UVM, System Verilog, Perl, Python
4w
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Staff ASIC Design Engineer
United States
$195k-$226k/yr OnsiteFull Time
5+ YOEMaster's in electrical/electronics/computer engineering, 5+ years VLSI experience with computer architecture, System Verilog/Verilog, Python/Perl scripting, RTL synthesis and verification, assembly programming, and strong communication skills.
System Verilog, Verilog, Python, Perl
2w
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Electrical Design Engineer (FPGA Firmware)
Milpitas, California, United States
$118k-$200k/yr OnsiteFull Time
2+ YOE2+ years FPGA firmware design experience; proficiency in VHDL/Verilog/System Verilog, FPGA tools (Synplify, ISE, Vivado, Quartus), simulation (VCS, Modelsim); lab equipment experience and strong communication.
Synplify, ISE, Vivado, Quartus, VCS, Modelsim, VHDL, Verilog, System Verilog, logic analyzer, oscilloscope
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