59 verilog jobs at 19 companies in Phoenix, AZ
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Senior Engineer I - Physical Design
Chandler, Arizona, United States
OnsiteFull Time
5+ YOE5+ years in physical design; place-and-route; low-power flows; EDA tools; scripting; Verilog/VHDL; strong debugging and communication.
Innovus, Fusion Compiler, Calibre, Redhawk, Starrcxt, Verilog, VHDL, TCL, PERL, Shell
1mo
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Senior Mixed-Signal Verification Engineer
Chandler, Arizona, United States
HybridFull Time
5+ YOE5+ years mixed-signal verification or modeling experience, B.S./M.S. in EE/CE, SystemVerilog/Verilog-AMS knowledge, strong communication and teamwork.
SystemVerilog, Verilog-AMS
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Sr Advanced Semiconductor Engineer
Phoenix or Glendale
HybridFull Time
5+ YOEBachelor's in a technical discipline, familiarity with VHDL/Verilog/SystemVerilog, 5+ years FPGA design/verification experience, and strong oral/written communication skills.
VHDL, Verilog, SystemVerilog, MATLAB, Simulink, LabVIEW, Perl, Shell, TCL, AMBA, I2C, SPI, Windows, LINUX, Microsoft Office, C, Xilinx, STA tools, Place & Route, synthesis
3w
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Lead, Digital Design Engineer (41438)
Londonderry or Tempe
OnsiteFull Time
9+ YOE9+ years firmware/FPGA (VHDL/Verilog) experience, experience with image/video processing, EM interfaces, test equipment, and translating system into firmware requirements.
VHDL, Verilog, Microchip, Xilinx, Altera (Intel), OrCAD, PSpice, Cadence Allegro, Git, Jira, Jenkins, DOORS, ModelSim, Oscilloscope, Logic Analyzer, Spectrum Analyzer
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FPGA Engineer (AZ, Phoenix)
Phoenix, Arizona, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Design, develop, test, and maintain FPGA IP cores and hardware security systems; RTL, C/C++, Python, VHDL/Verilog; FPGA tools; security clearance.
VHDL, Verilog, SystemVerilog, Python, C, C++, Tcl, Vivado, Questa, GHDL, Quartus Prime, Xilinx, Versal, AcE, AXI, Avalon
3d
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Senior Digital Verification Engineer
Chandler, Arizona, United States
OnsiteFull Time
3+ YOEBSEE with 8+ years, MSEE with 5+ years, or PhD with 3+ years in semiconductor industry; expertise in Verilog, SystemVerilog, UVM/OVM, verification methodologies, protocols, and automation scripting.
SystemVerilog, Universal Verification Methodology (UVM), OVM, Verilog, SystemVerilog Assertions (SVA), UPF, CPF, AMBA, I²C, SPI, UART, CAN, LIN, DDR, PCIe, Python, Perl, UNIX, Linux, HAPS, Palladium, Zebu, AI, LLM
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FPGA Engineer (Space)
Tempe, Arizona, United States
$105k-$165k/yr OnsiteFull Time
2+ YOEBachelors in EE/CE,2+ years FPGA design with Xilinx Vivado,SystemVerilog/VHDL/Verilog experience,ability to read schematics,good communication,US citizenship,travel up to 10%.
Xilinx Vivado, System Verilog, VHDL, Verilog, AMD/Xilinx ISE, Intel/Altera Quartus, Siemens/Mentor Graphics, Synopsys Synplify, TCL, Perl, Python, Linux, GitHub, Matlab, Claud Code, Copilot
2w
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FPGA Digital Engineer - 2
Chandler, Arizona, United States
$87k-$131k/yr OnsiteFull Time
2+ YOEBachelor's in EE/CE plus 2 years (or Master's), ability to obtain DoD Secret clearance, FPGA (VHDL/Verilog) experience, Vivado and simulation tool familiarity, and digital interface verification experience.
VHDL, Verilog, AMD Xilinx FPGAs, Vivado IDE, Questa, ModelSim, Vitis Unified IDE, C, C++, OSVVM, UVM
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Applications Engineer - FPGA Prototyping
San Diego or Austin or Boulder or Costa Mesa or Pasadena or Tempe or Wilsonville or Fremont
$167k-$334k/yr HybridFull Time
5+ YOE5+ years in design/verification/FPGA/ASIC or similar; BS/MS in EE/CE/CS; active experience with SystemVerilog/Verilog/VHDL, FPGA tools, scripting, simulation and customer-facing technical support.
SystemVerilog, Verilog, VHDL, SystemC, C/C++, Perl, Python, XML, JSON, proFPGA, HAPS, Xilinx Vivado, Altera Quartus, Questa, Incisive, VCS, OVM, UVM
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R&D Engineer Hardware 4
Chandler, Arizona, United States
$110k-$176k/yr OnsiteFull Time
6+ YOEMSEE or PhD preferred, 6+ years industry experience, expertise in mixed-signal/analog IC design, Cadence Virtuoso, SPICE simulators, Verilog, Synopsys Liberty, Python; silicon validation and documentation experience.
Cadence Virtuoso, ADE, Spectre, Hspice, Finesim, Verilog, Synopsys Liberty, Python
2mo
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Advanced ASIC FPGA Design Engineer for Crypto and Cross Domain Solutions
Scottsdale, Arizona, United States
$135k-$150k/yr OnsiteFull Time
3+ YOEBachelor's in EE/CE +5 years or Master's +3 years, proficiency in VHDL/Verilog/SystemVerilog, Vivado/Libero, FPGA timing closure, simulation (QuestaSim/ModelSim), and ability to obtain/maintain Secret clearance.
VHDL, Verilog, SystemVerilog, Vivado, Libero, QuestaSim, ModelSim, GitLab CI, GitLab, Tcl, Python, Bash, ILA, JTAG, AXI-Stream, AXI4
3w
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Sr. Logic Design Engineer
Santa Clara or Phoenix or Hillsboro
$142k-$200k/yr HybridFull Time
4+ YOEBachelor's in Electrical/Computer Engineering with 4+ years (or Master's w/2+, PhD w/1+) and experience in RTL/System Verilog, front-end lint/synthesis tools, VCS/Verdi, UPF, CDC and IP environment.
System Verilog, VCS, Verdi, UPF, Lint, Synthesis
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FPGA Engineer (Space)
Tempe, Arizona, United States
$133k-$210k/yr OnsiteFull Time
6+ YOEBachelor's in EE/CE,6+ years FPGA design experience with Xilinx Vivado,proficient in Verilog/SystemVerilog/VHDL,EDA tools experience,ability to debug hardware,US citizenship required,ability to travel up to 10%.
Verilog, SystemVerilog, VHDL, AMD/Xilinx ISE, Vivado, Intel/Altera Quartus, Siemens/Mentor Graphics, Synopsys Synplify, TCL, Perl, Python, GitHub, Matlab, Linux, UVM
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DFT Engineer (CE-64000920)
Austin or Chandler or Greensboro
HybridFull Time
2+ YOEMSEE with 2+ years or BS with relevant experience; hands-on ASIC DFT design and verification; experience with FastScan, TestKompress, TetraMAX, Test Compiler; MBIST, scan/ATPG, Verilog/SystemVerilog/VHDL; scripting (Perl, Python, TCL); strong communication.
FastScan, TestKompress, TetraMAX, Test Compiler, Verilog, SystemVerilog, VHDL, Perl, Python, TCL
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Staff Engineer, Design Verification Engineering
Chandler, Arizona, United States
$172k-$199k/yr HybridFull Time
4+ YOEMaster's degree in Electrical Engineering, Materials Engineering, or Physics with 4 years in design verification; or Bachelor's with 6 years; strong SystemVerilog/UVM skills; Verilog-RTL, mixed-signal verification; Xcelium/VCS; scripting (Perl/Python/C).
SystemVerilog, UVM, Verilog-AMS, Cadence AMS, Xcelium, VCS, Perl, Python, C
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Principal Design Engineer
Chandler or Phoenix or Raleigh or Durham
OnsiteFull Time
10+ YOEBSEE/MSEE with 10+ years experience in precision analog/mixed-signal design; transistor-level design ownership, system-to-block requirements translation, DFT/simulation, EMR of product development; familiarity with Cadence AMS, JAMA, GIT; System Verilog desired.
Cadence Analog and Mixed Signal Tool Suite, JAMA, GIT, system Verilog
2w
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Hardware Designer
Phoenix or United States
RemoteFull Time
5+ YOE5+ years electronics design experience, Bachelors in Electrical/Computer Engineering, high-speed PCB and system design expertise, familiarity with FPGA and signal integrity, bench bring-up and test experience.
LTSpice, OrCAD Capture CIS, Cadence CIS, Cadence Allegro, Verilog, RTL, HLS, optical test set, signal analyzer, oscilloscope, VNA, signal generator
2d
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FPGA Team Lead
Phoenix, Arizona, United States
$80-$90/hr RemoteFull Time
10+ YOE2+ MgmtBachelor's degree in a technical field, 10+ years of FPGA or related engineering experience, 2+ years leading technical teams, VHDL or UVM experience, and U.S. citizenship or permanent residency.
VHDL, UVM, Quartus, Vivado, ModelSim, Questa, Python, Tcl, DOORS, ClearQuest, generative AI
1mo
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Mixed-Signal Engineer
Tempe or San Francisco or Phoenix
$130k-$170k/yr HybridFull Time
4+ YOEBS/MS in EE,4+ years mixed-signal hardware design,high-speed PCB and analog fundamentals,lab experience with oscilloscopes and analyzers,and experience interfacing data converters to FPGAs.
Altium, Cadence Allegro, JESD204, SerDes, VHDL, Verilog, SystemVerilog, Xilinx, AMD, Intel, oscilloscope, spectrum analyzer, network analyzer
2mo
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Senior Design Verification Engineer (eInfochips Inc)
Minneapolis or Phoenix
OnsiteFull Time
Bachelor’s or Master’s in EE/CE or related; strong SystemVerilog and UVM skills; scripting with Python/Perl/Tcl; experience with Cadence Xcelium, Synopsys VCS or Siemens Questa; knowledge of constrained-random verification, SVA, functional coverage and AMBA protocols.
UVM, SystemVerilog, Python, Perl, Tcl, Cadence Xcelium, Synopsys VCS, Siemens Questa, Cadence Palladium, C, SVA, UPF, CPF, Real Number Models (RNM), AMBA (AXI/AHB/APB)
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