93 verilog jobs at 26 companies in Arizona
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Senior Engineer I - Physical Design
Chandler, Arizona, United States
OnsiteFull Time
5+ YOE5+ years in physical design; place-and-route; low-power flows; EDA tools; scripting; Verilog/VHDL; strong debugging and communication.
Innovus, Fusion Compiler, Calibre, Redhawk, Starrcxt, Verilog, VHDL, TCL, PERL, Shell
1w
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Digital and Mixed Signal IC Design/DV Engineer
Tucson, Arizona, United States
OnsiteFull Time
1+ YOEMaster's degree in Electrical Engineering, 1+ years of relevant experience, digital logic design knowledge, and familiarity with Verilog, SystemVerilog, VHDL, and simulators.
Verilog, SystemVerilog, VHDL, DMS, AMS, UVM, RTL, FSM, GLS, Gates+SDF, PVT
1mo
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Senior Mixed-Signal Verification Engineer
Chandler, Arizona, United States
HybridFull Time
5+ YOE5+ years mixed-signal verification or modeling experience, B.S./M.S. in EE/CE, SystemVerilog/Verilog-AMS knowledge, strong communication and teamwork.
SystemVerilog, Verilog-AMS
1d
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Semiconductor Engineer I
Phoenix, Arizona, United States
HybridFull Time
0.5+ YOEBachelor’s degree in a technical discipline and at least 6 months of ASIC/FPGA design language experience with VHDL, Verilog, or SystemVerilog; communication skills required.
VHDL, Verilog, SystemVerilog, HDL, Microsoft Office, UNIX, Linux, DO-254
3w
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Lead, Digital Design Engineer (41438)
Londonderry or Tempe
OnsiteFull Time
9+ YOE9+ years firmware/FPGA (VHDL/Verilog) experience, experience with image/video processing, EM interfaces, test equipment, and translating system into firmware requirements.
VHDL, Verilog, Microchip, Xilinx, Altera (Intel), OrCAD, PSpice, Cadence Allegro, Git, Jira, Jenkins, DOORS, ModelSim, Oscilloscope, Logic Analyzer, Spectrum Analyzer
2mo
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Digital Design Engineer
Tucson, Arizona, United States
$165k/yr OnsiteFull Time
Bachelor's in electrical engineering or related, proven digital design experience, FPGA/ASIC knowledge, VHDL or Verilog proficiency, strong problem-solving and communication skills.
FPGA, ASIC, VHDL, Verilog
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FPGA Engineer (AZ, Phoenix)
Phoenix, Arizona, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Design, develop, test, and maintain FPGA IP cores and hardware security systems; RTL, C/C++, Python, VHDL/Verilog; FPGA tools; security clearance.
VHDL, Verilog, SystemVerilog, Python, C, C++, Tcl, Vivado, Questa, GHDL, Quartus Prime, Xilinx, Versal, AcE, AXI, Avalon
2mo
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FPGA Engineer with DSP Emphasis - Tucson, AZ
Tucson, Arizona, United States
$79k-$237k/yr OnsiteFull Time
3+ YOEABET-accredited BS in EE or CE; 3+ years; VHDL/Verilog; FPGA design; DSP; Linux; Python/C++; ability to obtain Top Secret/SCI clearance.
VHDL, Verilog, Python, C, C++, Linux, Git, ClearCase, Bitbucket
1w
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Senior Digital Verification Engineer
Chandler, Arizona, United States
OnsiteFull Time
3+ YOEBSEE with 8+ years, MSEE with 5+ years, or PhD with 3+ years in semiconductor industry; expertise in Verilog, SystemVerilog, UVM/OVM, verification methodologies, protocols, and automation scripting.
SystemVerilog, Universal Verification Methodology (UVM), OVM, Verilog, SystemVerilog Assertions (SVA), UPF, CPF, AMBA, I²C, SPI, UART, CAN, LIN, DDR, PCIe, Python, Perl, UNIX, Linux, HAPS, Palladium, Zebu, AI, LLM
1w
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FPGA Design Engineer II
Tucson, Arizona, United States
$69k-$131k/yr OnsiteFull Time
2+ YOESTEM degree and 2+ years of relevant experience; VHDL or Verilog coding; experience with Xilinx or Microsemi devices and flow tools; U.S. citizenship and active or interim security clearance.
Xilinx, Altera, Microsemi, VHDL, Verilog, SystemVerilog, UVM, Veloce, ARM, MicroBlaze, Nios
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FPGA Engineer (Space)
Tempe, Arizona, United States
$105k-$165k/yr OnsiteFull Time
2+ YOEBachelors in EE/CE,2+ years FPGA design with Xilinx Vivado,SystemVerilog/VHDL/Verilog experience,ability to read schematics,good communication,US citizenship,travel up to 10%.
Xilinx Vivado, System Verilog, VHDL, Verilog, AMD/Xilinx ISE, Intel/Altera Quartus, Siemens/Mentor Graphics, Synopsys Synplify, TCL, Perl, Python, Linux, GitHub, Matlab, Claud Code, Copilot
3w
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FPGA Digital Engineer - 2
Chandler, Arizona, United States
$87k-$131k/yr OnsiteFull Time
2+ YOEBachelor's in EE/CE plus 2 years (or Master's), ability to obtain DoD Secret clearance, FPGA (VHDL/Verilog) experience, Vivado and simulation tool familiarity, and digital interface verification experience.
VHDL, Verilog, AMD Xilinx FPGAs, Vivado IDE, Questa, ModelSim, Vitis Unified IDE, C, C++, OSVVM, UVM
1mo
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Applications Engineer - FPGA Prototyping
San Diego or Austin or Boulder or Costa Mesa or Pasadena or Tempe or Wilsonville or Fremont
$167k-$334k/yr HybridFull Time
5+ YOE5+ years in design/verification/FPGA/ASIC or similar; BS/MS in EE/CE/CS; active experience with SystemVerilog/Verilog/VHDL, FPGA tools, scripting, simulation and customer-facing technical support.
SystemVerilog, Verilog, VHDL, SystemC, C/C++, Perl, Python, XML, JSON, proFPGA, HAPS, Xilinx Vivado, Altera Quartus, Questa, Incisive, VCS, OVM, UVM
1mo
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R&D Engineer Hardware 4
Chandler, Arizona, United States
$110k-$176k/yr OnsiteFull Time
6+ YOEMSEE or PhD preferred, 6+ years industry experience, expertise in mixed-signal/analog IC design, Cadence Virtuoso, SPICE simulators, Verilog, Synopsys Liberty, Python; silicon validation and documentation experience.
Cadence Virtuoso, ADE, Spectre, Hspice, Finesim, Verilog, Synopsys Liberty, Python
3mo
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Advanced ASIC FPGA Design Engineer for Crypto and Cross Domain Solutions
Scottsdale, Arizona, United States
$135k-$150k/yr OnsiteFull Time
3+ YOEBachelor's in EE/CE +5 years or Master's +3 years, proficiency in VHDL/Verilog/SystemVerilog, Vivado/Libero, FPGA timing closure, simulation (QuestaSim/ModelSim), and ability to obtain/maintain Secret clearance.
VHDL, Verilog, SystemVerilog, Vivado, Libero, QuestaSim, ModelSim, GitLab CI, GitLab, Tcl, Python, Bash, ILA, JTAG, AXI-Stream, AXI4
4w
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Sr. Logic Design Engineer
Santa Clara or Phoenix or Hillsboro
$142k-$200k/yr HybridFull Time
4+ YOEBachelor's in Electrical/Computer Engineering with 4+ years (or Master's w/2+, PhD w/1+) and experience in RTL/System Verilog, front-end lint/synthesis tools, VCS/Verdi, UPF, CDC and IP environment.
System Verilog, VCS, Verdi, UPF, Lint, Synthesis
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FPGA Engineer (Space)
Tempe, Arizona, United States
$133k-$210k/yr OnsiteFull Time
6+ YOEBachelor's in EE/CE,6+ years FPGA design experience with Xilinx Vivado,proficient in Verilog/SystemVerilog/VHDL,EDA tools experience,ability to debug hardware,US citizenship required,ability to travel up to 10%.
Verilog, SystemVerilog, VHDL, AMD/Xilinx ISE, Vivado, Intel/Altera Quartus, Siemens/Mentor Graphics, Synopsys Synplify, TCL, Perl, Python, GitHub, Matlab, Linux, UVM
3w
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FPGA Digital Engineer - 2
Chandler, Arizona, United States
$87k-$131k/yr OnsiteFull Time
2+ YOEBachelor's in EE/CE or related with 2 years experience (or Master's); ability to obtain DoD Secret clearance; FPGA design experience (VHDL/Verilog), Vivado, simulation and verification skills; familiarity with Xilinx devices and digital interfaces.
Vivado IDE, Questa/ModelSim, Vitis Unified IDE, AMD Xilinx FPGAs and SoCs, VHDL, Verilog, C, C++, OSVVM, UVM
2mo
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DFT Engineer (CE-64000920)
Austin or Chandler or Greensboro
HybridFull Time
2+ YOEMSEE with 2+ years or BS with relevant experience; hands-on ASIC DFT design and verification; experience with FastScan, TestKompress, TetraMAX, Test Compiler; MBIST, scan/ATPG, Verilog/SystemVerilog/VHDL; scripting (Perl, Python, TCL); strong communication.
FastScan, TestKompress, TetraMAX, Test Compiler, Verilog, SystemVerilog, VHDL, Perl, Python, TCL
3mo
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Staff Engineer, Design Verification Engineering
Chandler, Arizona, United States
$172k-$199k/yr HybridFull Time
4+ YOEMaster's degree in Electrical Engineering, Materials Engineering, or Physics with 4 years in design verification; or Bachelor's with 6 years; strong SystemVerilog/UVM skills; Verilog-RTL, mixed-signal verification; Xcelium/VCS; scripting (Perl/Python/C).
SystemVerilog, UVM, Verilog-AMS, Cadence AMS, Xcelium, VCS, Perl, Python, C
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