380 verilog jobs at 80 companies in Texas
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Senior Silicon Engineer
Redmond or Mountain View or Santa Clara or Austin or Raleigh or Hillsboro or Boise
$120k-$235k/yr HybridFull Time
5+ YOEExperience verifying silicon using UVM/C, strong RTL and SoC verification background, proficiency with Verilog/System Verilog, and relevant EE/CS/CE degree or equivalent experience.
UVM, C, Verilog, System Verilog, Microsoft Excel
1mo
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Silicon IP Verification Methodology Lead (785271)
Austin, Texas, United States
HybridFull Time
15+ YOE15+ years IP/SoC verification experience; expertise in RTL, Verilog, System Verilog, UVM/OVM, formal methods, VCS/Xcelium, Perl/Python scripting, synthesis/STA/DFT, and leadership of distributed teams.
RTL, Verilog, System Verilog, UVM, OVM, VCS, Xcelium, Perl, Python, Design-For-Test (DFT)
2mo
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Sr. Engineer, CPU RTL Design
Austin or Santa Clara
$100k-$500k/yr HybridFull Time
Experience in CPU microarchitecture, RTL coding (Verilog/VHDL), and cross-functional collaboration.
Verilog, VHDL, Simulation Tools, Synthesis Tools, Power Analysis Tools
2mo
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Senior/Staff Design Engineer
Santa Clara or Richardson or Austin
$69k-$202k/yr OnsiteFull Time
2+ YOEBachelor's (3–7 yrs) or Master's (2–5 yrs); knowledge of CPU microarchitecture, System Verilog/Verilog/VHDL, simulators, timing/power; scripting in Perl or Python; experience with RISC-V/ARM/MIPS preferred.
System Verilog, Verilog, VHDL, Perl, Python, RISC-V, ARM, MIPS
3d
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Sr. Silicon Design Engineer
Austin, Texas, United States
$106k-$182k/yr OnsiteFull Time
1+ YOEMaster's degree in computer, electrical, electronics, or related engineering; 1 year related experience; skills in C, C++, Python, CPU/GPU/SoC architecture, ASIC design, Verilog, System Verilog, VHDL, verification, and data structures.
C, C++, Python, Verilog, SystemVerilog, VHDL
3w
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FPGA Engineer Intern (Summer 2027 - Austin)
Austin or Chicago
OnsiteInternship
Student in Computer/Electrical Engineering (BS/MS/PhD) graduating Dec 2027–Jun 2028; hands-on FPGA/ASIC digital design experience; VHDL/Verilog/System Verilog experience; strong engineering instincts and teamwork skills.
FPGAs, ASICs, VHDL, Verilog, System Verilog
1mo
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Interconnect Design Engineer
Santa Clara or Cambridge or Austin or Boston
OnsiteFull Time
Staff-level hardware engineer with experience designing interconnects, cache/coherency, RTL generators using Chisel/Scala; proficiency in Verilog/System Verilog/VHDL and hardware-software engineering practices; BS/MS in EE/CE/CS or equivalent.
Chisel, Scala, FIRRTL, Verilog, System Verilog, VHDL, TileLink, RISC-V, NoC, AXI, AHB, APB, CHI, Bluespec, Git, GitHub, Jira, Confluence
1mo
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Sr. FPGA Engineer
Singapore or Austin or Hsinchu or Shanghai or Shenzhen
OnsiteFull Time
8+ YOEBSEE/BSCE with 8+ years FPGA design and 6+ years SoC design experience. Experience with RTL/Verilog/System Verilog, FPGA bring-up, timing constraints, Xilinx Vivado/ISE, Intel Quartus Prime Pro, git, Python, and YAML.
Xilinx Vivado, ISE, Intel Quartus Prime Pro, Cadence, git, Python, YAML, Verilog, System Verilog, C, AMD VU19P, Stratix 10, AMD FPGA, Siemens proFPGA, ARM MPS4, I2C, I3C, MSPI, UART, USB
3mo
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DDR Design Engineer
Austin, Texas, United States
OnsiteFull Time
Bachelor's in Electrical Engineering; RTL design with Verilog/SystemVerilog; timing constraints; DFT; DDR PHY knowledge.
Verilog, SystemVerilog, DFT, RTL design, Timing analysis, Unified Power Format
1mo
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Digital IC Design Engineer (INT TRX)
Dallas, Texas, United States
OnsiteFull Time
5+ YOE5+ years experience in digital circuit design with Verilog; understanding of analog functionality and systematic problem solving.
Verilog, System Verilog
2mo
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Staff Digital Design Engineer – SOC Low Power, Clocking & Integration
Austin, Texas, United States
$143k-$266k/yr HybridFull Time
10+ YOEBS/MS in EE, 10+ years digital CMOS IC design experience, Verilog/System Verilog expertise, low-power (UPF/CPF) and clocking/CDC/RDC knowledge, AXI/AHB/APB experience, scripting (Python/Perl/Tcl), and leadership of small design teams.
Verilog, System Verilog, UPF, CPF, AXI, AHB, APB, C, Python, Perl, Tcl, Perforce, Git, Methodics
2mo
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Staff Digital Design Engineer – SOC Low Power, Clocking & Integration
Austin, Texas, United States
$143k-$266k/yr HybridFull Time
10+ YOEBS/MS in Electrical Engineering, 10+ years digital CMOS IC design experience, expertise in Verilog/System Verilog, UPF/CPF, AXI/AHB/APB, RTL design, synthesis, timing, power analysis, simulation, scripting (Python/Perl/Tcl), and leading small teams.
Verilog, System Verilog, UPF, CPF, AXI, AHB, APB, RISC-V, C, Python, Perl, Tcl, Perforce, Git, Methodics
2mo
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Digital IP Principal Verification Engineer
Austin, Texas, United States
OnsiteFull Time
6+ YOEBachelors in EE/CE/CS required, 6+ years IP/SoC design or verification experience, strong Verilog/System Verilog/UVM skills, test planning and debug, SVA and formal verification, familiarity with Python/C/C++/Perl/TCL and ARM AMBA a plus; AI use proficiency.
Verilog, System Verilog, UVM, System Verilog Assertion (SVA), Python, C/C++, Perl, TCL, ARM AMBA®, AI
2mo
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FPGA Engineer Engineer (eInfochips)
San Jose or Austin
OnsiteFull Time
9+ YOE9+ years experience; proficient in Verilog/System Verilog, EDA tools (VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus), IPXACT, UPF, PCIe/AXI/APB, ARM fabric; scripting with Python/Tcl/Perl; timing signoff and clock-crossing expertise.
Verilog, System Verilog, Python, Tcl, Perl, VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus, IPXACT, UPF
2w
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2027 Internship- Hardware Engineer (FPGA)
Austin or New York City
OnsiteInternship
Currently pursuing a Masters in Electrical Engineering; experience with SystemVerilog/Verilog, Python or C++, basic network protocols, strong problem solving and communication.
SystemVerilog, Verilog, Python, C++, HackerRank
3mo
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HBM Design Engineering Lead - MTS/SMTS/DMTS
Richardson, Texas, United States
OnsiteFull Time
Lead cross-functional HBM design programs; strong DRAM/HBM, CMOS design knowledge; RTL/Verilog experience; excellent communication and leadership.
Verilog, RTL, HSPICE, FastSpice, CMOS, DRAM
1w
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Security IP Design Engineer
Austin, Texas, United States
$162k-$219k/yr HybridFull Time
Bachelor's or graduate degree in computer science or electrical/computer engineering, with advanced Verilog RTL, security hardware, SoC architecture, EDA, scripting, and SystemVerilog experience.
Verilog, RTL, EDA, AXI, AHB, Perl, Python, TCL, SystemVerilog, UVM, OVM, Portable Stimulus, UPF, CDC, RDC, LINT
3mo
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FPGA Engineer (TX, Austin)
Austin, Texas, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Design, develop, test, and maintain FPGA IP cores and systems; experience with RTL, C/C++, Python, VHDL/Verilog; FPGA toolchains; security clearance.
RTL, C/C++, Python, VHDL, Verilog, Tcl, Vivado, GHDL, Questa, Quartus Prime, Zynq, Versal, Altera, Stratix, AXI, ACE, Avalon, cocotb, pyuvm
2mo
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Sr. RTL Design Engineer (Silicon Engineering)
Irvine or Austin or Redmond or Sunnyvale
$160k-$225k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE/CS; 5+ years RTL implementation; Verilog/SystemVerilog; ASIC/SoC integration; clock domain crossing; scripting and EDA tools.
Verilog, SystemVerilog, HDL simulators, HDL Lint tools, Python, EDA tools, Scripting, AXI, AHB
2mo
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Senior Power Analysis and Optimization Engineer
Santa Clara or Austin
$136k-$265k/yr OnsiteFull Time
5+ YOEMS with 5+ years or PhD with 3+ years in EE/CE/CS; strong power design knowledge; Verilog; experience with power tools; Python/Perl/C++.
Verilog, PowerArtist, PrimePower, PrimePower RTL, RTL Architect, Python, Perl, C++
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