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Hardware Engineer – VHDL RTL Digital Logic
Pullman, Washington, United States
$98k-$144k/yr OnsiteFull Time
Experience designing VHDL RTL digital logic for FPGAs, writing testbenches and verification, system specification and documentation, Ethernet and precise timing knowledge (PTP/IRIG-B), and project leadership.
VHDL, FPGA, Ethernet (IEEE 802.3), PTP (IEEE 1588), IRIG-B
2mo
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Junior Engineer, FPGA
Princeton, New Jersey, United States
$60k-$62k/yr OnsiteFull Time
FPGA design with Verilog/VHDL or HLS; testbench development; target/retarget FPGA designs; knowledge of Verilog, VHDL, SystemVerilog and C; experience with timing closure and Xilinx boards; document design data sheets.
Verilog, VHDL, SystemVerilog, C, Xilinx tools, FPGA
2mo
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Full Time Raytheon 2026 - Multi-Product Power & Digital FPGA Engineer II
McKinney, Texas, United States
$69k-$131k/yr OnsiteFull Time
1+ YOEMaster's in electrical engineering or related STEM; 12 months or less relevant experience; experience with analog/digital electronics, VHDL/FPGA, circuit design/analysis; preferred GPA 3.0; familiarity with VHDL/Verilog and lab equipment.
VHDL, Verilog, FPGA, Electrical Components, Digital Signal Processing, PCB design
3w
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Manager Digital Engineering 1
San Diego, California, United States
$133k-$200k/yr OnsiteFull Time
5+ YOEManager for digital/VHDL engineering team; requires BS+5yrs or MS+3yrs in STEM, significant VHDL and FPGA experience, active Secret clearance, leadership and strong communication skills, and ability to work onsite in Rancho Carmel.
VHDL, Versal, Zynq, Kintex, Ultrascale, Vivado, Quartus, QuestaSim
2mo
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Sr. Engineer, CPU RTL Design
Austin or Santa Clara
$100k-$500k/yr HybridFull Time
Experience in CPU microarchitecture, RTL coding (Verilog/VHDL), and cross-functional collaboration.
Verilog, VHDL, Simulation Tools, Synthesis Tools, Power Analysis Tools
3mo
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CPU Power Management Microarchitect/RTL Engineer
Santa Clara, California, United States
OnsiteFull Time
3+ YOEBS plus 3+ years in microprocessor architecture, Verilog/VHDL, RTL design, and debugging.
Verilog, VHDL, C, C++, Python, Perl
3mo
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ASIC Design Engineer III
United States
$82k-$198k/yr RemoteFull Time
3+ YOEBachelor's with 5-7 yrs or Master's with 3-5 yrs or PhD with 0-2 yrs; Secret clearance; 3+ yrs VHDL targeting Xilinx; 3 yrs Cadence Virtuoso; 5 yrs VHDL/Verilog; 3 yrs ModelSim/QuestaSim.
VHDL, Verilog, SystemVerilog, ModelSim, QuestaSim, Cadence Virtuoso, Synopsys Genus, Xcelium
2mo
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Engineer - FPGA
State College, Pennsylvania, United States
OnsiteFull Time
3+ YOEFPGA design/development, RTL/VHDL/Verilog, Linux experience, and cross-disciplinary collaboration required.
Vivado, Libero, ModelSim, cocotb, Git, C, C++, Python, VHDL, Verilog, SystemVerilog
2mo
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Electrical Engineer
Vancouver, Washington, United States
$93k-$144k/yr OnsiteFull Time
4+ YOEDesigns electrical hardware, FPGA/ASIC, Verilog/VHDL, debugging, testing, leadership of project teams.
FPGA, Verilog, VHDL, C++, Electrical Engineering
3mo
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FPGA Design Engineer - Avionics
Saratoga, California, United States
$150k-$250k/yr OnsiteFull Time
5+ YOE5+ years FPGA design experience; SystemVerilog/VHDL; AXI interfaces; timing closure; radiation-tolerant design knowledge.
SystemVerilog, VHDL, AXI, SPI, I2C, GPIO, Python, TCL, Shell scripting, Makefiles, VCS, QuestaSim
3mo
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Senior/Principal FPGA Design Engineer
Calabasas or Burnaby or Austin
$139k-$232k/yr OnsiteFull Time
8+ YOEBachelors or Masters in EE/CE; 8+ years in FPGA; strong VHDL/SystemVerilog; excellent communication; team leadership potential.
VHDL, SystemVerilog, Ethernet, PCIe, Interlaken, DDR5, RLDRAM3, SerDes, Tcl, Perl, Python
2mo
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FPGA Engineer (IL, Schaumburg)
Schaumburg, Illinois, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Experience with RTL, C/C++, Python, VHDL/Verilog; hardware security; FPGA design and verification; system integration; cryptography concepts.
C/C++, Python, VHDL, Verilog, Tcl, Vivado, Questa, Quartus Prime, GHDL, Xilinx, Versal, Agilex, AXI, Avalon, cocotb, pyuvm
2mo
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Sr Digital System Designer
Palo Alto, California, United States
$145k-$160k/yr OnsiteFull Time
5+ YOEBachelor’s or Master’s in EE/CS; 5+ years digital design; SystemVerilog/VHDL; FPGA experience; Python; cross-team collaboration.
SystemVerilog, VHDL, FPGA (Xilinx), Python, Cocotb, High Level Synthesis (Xilinx Vitis)
3mo
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Technical Lead, Simulation and Modeling
Ann Arbor, Michigan, United States
OnsiteFull Time
MS in Computer Engineering; familiarity with Gem5, ASTRA-sim or similar; Verilog/VHDL RTL with VCS; experience with AI/workload simulations.
Gem5, ASTRA-sim, Verilog, VHDL, VCS
2mo
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Project Engineer 1 - New College Grad 2025 - 2026 (E&C - Forth Worth, TX)
Fort Worth, Texas, United States
OnsiteFull Time
Bachelor’s degree or higher in Electrical, Mechanical, Systems, or Industrial Engineering; experience with CAD/SolidWorks/Revit/Python/SCADA/MATLAB/VHDL.
CAD, SolidWorks, Revit, Python, SCADA, MATLAB, VHDL
3mo
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FPGA Logic Design Engineer 4
Duluth, Georgia, United States
OnsiteFull Time
7+ YOESenior FPGA design engineer with 7+ years hardware experience, proficient in VHDL/Verilog, FPGA life-cycle, and DO-254 processes.
VHDL, Verilog, FPGA Toolchain, Version Control
3w
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Sr. FPGA Engineer II
Chantilly, Virginia, United States
$143k-$239k/yr OnsiteFull Time
8+ YOEBachelor's in computer or electrical engineering with 8+ years experience; FPGA firmware design with VHDL; ability to obtain U.S. government security clearance.
VHDL, Xilinx, AMD Versal, C, Python, MATLAB, DDR4, Aurora, AXI Stream, AXI Memory Mapped, Altium Designer
2mo
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FPGA Engineer
Chicago, Illinois, United States
$175k-$225k/yr HybridFull Time
FPGA development experience (Verilog/VHDL), functional verification, static timing, PCIe; programming in C++/Python; strong problem-solving and collaboration.
Verilog, VHDL, PCIe, C++, Python, Synopsys, Riviera, ModelSim, QuestaSim
2mo
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Senior Engineer I - Physical Design
Chandler, Arizona, United States
OnsiteFull Time
5+ YOE5+ years in physical design; place-and-route; low-power flows; EDA tools; scripting; Verilog/VHDL; strong debugging and communication.
Innovus, Fusion Compiler, Calibre, Redhawk, Starrcxt, Verilog, VHDL, TCL, PERL, Shell
2mo
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Firmware Engineering Lead
Cypress or Torrance
OnsiteFull Time
10+ YOEBachelor's degree in a technical discipline; 10+ years experience; Verilog/VHDL; FPGA experience (AMD/Altera); US government security clearance.
Verilog, VHDL, AMD FPGA, Altera FPGA, Jira, Bitbucket, Confluence
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