27 asic jobs at 15 companies in Arizona
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Senior ASIC Methodology Engineer - LPU Division
California or Texas or North Carolina or Arizona or Oregon or Massachusetts or United States
$152k-$288k/yr RemoteFull Time
5+ YOEBachelor's or Master's in CS/CE/EE (or equivalent), 5+ years industry experience, ASIC methodology and RTL/verification exposure, Python/Perl/Make/shell skills, experience with AI frameworks and strong communication.
Python, Perl, Make, Shell
1mo
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ASIC and Custom Silicon Sales Leader
Santa Clara or Hillsboro or Folsom or Phoenix
$454k-$641k/yr HybridFull Time
12+ YOE5+ MgmtBachelor's in EE/CE or related; 12+ years in semiconductor/ASIC/SoC/foundry/silicon solution sales; 5+ years people management; deep ASIC market knowledge, executive relationships, financial acumen, and ability to travel globally.
2mo
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Advanced ASIC FPGA Engineer- (Sign-on Bonus Available)
Scottsdale, Arizona, United States
$123k-$136k/yr HybridFull Time
5+ YOEBachelor's in Electrical/Computer Engineering (or related) with 5+ years experience (or Master's+3), U.S. citizenship, ability to obtain TS/SCI, proficiency in VHDL/Verilog, scripting (Tcl/Python/Perl), and ASIC/FPGA design and verification.
Microsoft Office, VHDL, Verilog, Tcl, Python, Perl, Xilinx, Microchip, ISE, Vivado, Libero, Precision, Synplify, QuestaSim, UVM, Questa CDC, Oscilloscope, Logic Analyzer, ChipScope, SystemVerilog, SVA, OVM
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ASIC Packaging Signal/Power Integrity Hardware Engineering Technical Lead (Remote)
San Jose or Research Triangle Park or Acton or Dallas or Tempe or Cary or Carlsbad or Colorado Springs
$184k-$264k/yr RemoteFull Time
3+ YOEBachelor's/MS/PhD in Electrical Engineering with 3+ to 8+ years SI/PI experience; expertise in high-speed design, SI/PI simulation, layout review, SPICE; mentoring and leadership experience.
Cadence Sigrity, Ansys HFSS, Keysight ADS, Cadence APD, Ansys EM, SPICE, Vector Network Analysis, IBIS
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Digital Design Engineer 4
Tucson, Arizona, United States
$175k/yr OnsiteFull Time
5+ YOEBachelor's in electrical engineering, 5+ years digital design experience, proficiency with FPGA and ASIC design, DSP knowledge, strong problem-solving and communication skills.
FPGA, ASIC
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Principal Engineer
Chandler, Arizona, United States
$174k/yr OnsiteFull Time
5+ YOEBachelor's degree in electrical, electronic, or computer engineering and 5 years of progressive experience. Requires ARM, SystemVerilog, UVM, ASIC verification, SOC testbench, simulations, regression management, and C-based testing.
ARM, I2C, SPI, SPMI, UART, SOC Testbench, SystemVerilog, UVM, GLS, ASIC, C
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Section Lead-Effector Digital Products
Tucson, Arizona, United States
$108k-$205k/yr OnsiteFull Time
8+ YOESTEM degree and 8+ years of relevant experience in FPGA or ASIC design/verification, radar hardware integration and test, digital CCA design, signal processing, or system architecture; active Secret clearance required.
FPGA, ASIC, VHDL, PCIe, Ethernet, I2C, SPI, UART
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Staff Digital Systems Engineer
Phoenix, Arizona, United States
$185k-$202k/yr OnsiteFull Time
10+ YOEBachelor's in EE/CE, 10+ years designing FPGA/ASIC/SoC-based digital hardware, board bring-up and lab debug, high-speed interface and timing analysis, signal integrity collaboration, strong communication and leadership.
FPGA, ASIC, DDR, PCIe, Ethernet, SerDes, LVDS, SPI, I2C, Linux
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Pre-Silicon Diagnostics Engineer
Arizona or Bloomington or Fort Collins
$106k-$243k/yr RemoteFull Time
4+ YOE4+ years experience in diagnostics/validation/firmware/embedded software for ASICs; proficiency in object-oriented programming, Python, Linux; strong debugging, networking fundamentals, and communication skills.
Python, Linux, UVM, Verilog, SystemVerilog
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Pre-Silicon Diagnostics Engineer
Arizona or Bloomington or Fort Collins
$106k-$243k/yr RemoteFull Time
4+ YOEDevelop diagnostics and emulator-based validation for ASICs, proficient in Python,OOP,Linux,knowledge of high-speed networking;4+ years experience;strong written and verbal English.
Python, Linux, UVM, Verilog, SystemVerilog
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Pre-Silicon Diagnostics Engineer
Arizona or Bloomington or Fort Collins
$106k-$243k/yr RemoteFull Time
4+ YOEExperience in diagnostics/validation/firmware/embedded software for ASICs, 4+ years experience, proficiency in object-oriented programming, Python, Linux, networking fundamentals, strong debug and communication skills.
Python, Linux, UVM, Verilog, SystemVerilog
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Applications Engineer - FPGA Prototyping
San Diego or Austin or Boulder or Costa Mesa or Pasadena or Tempe or Wilsonville or Fremont
$167k-$334k/yr HybridFull Time
5+ YOE5+ years in design/verification/FPGA/ASIC or similar; BS/MS in EE/CE/CS; active experience with SystemVerilog/Verilog/VHDL, FPGA tools, scripting, simulation and customer-facing technical support.
SystemVerilog, Verilog, VHDL, SystemC, C/C++, Perl, Python, XML, JSON, proFPGA, HAPS, Xilinx Vivado, Altera Quartus, Questa, Incisive, VCS, OVM, UVM
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Senior Digital Engineer
Chandler, Arizona, United States
OnsiteFull Time
5+ YOE5+ years digital design experience, degree in electrical/computer discipline, fluent Verilog/SystemVerilog, ASIC methodology, lint/CDC/RDC experience, RTL and gate-level debug, English proficiency, willing to travel.
Verilog, SystemVerilog, Lint, CDC, RDC, UPF, UVM, AMBA, I2C, STA
2w
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Senior Design Verification Engineer
Tempe or Independence
$156k-$291k/yr RemoteFull Time
8+ YOE8+ years design verification experience with UVM, SystemVerilog, RTL verification for FPGA/ASIC, Bachelor's in EE/CE, US citizenship, ability to obtain Secret clearance, familiarity with Questa/Xcelium/VCS and AI verification tools.
Universal Verification Methodology (UVM), SystemVerilog, VHDL, Verilog, Questa, Xcelium, VCS, Jira
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DFT Engineer (CE-64000920)
Austin or Chandler or Greensboro
HybridFull Time
2+ YOEMSEE with 2+ years or BS with relevant experience; hands-on ASIC DFT design and verification; experience with FastScan, TestKompress, TetraMAX, Test Compiler; MBIST, scan/ATPG, Verilog/SystemVerilog/VHDL; scripting (Perl, Python, TCL); strong communication.
FastScan, TestKompress, TetraMAX, Test Compiler, Verilog, SystemVerilog, VHDL, Perl, Python, TCL
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Principal Engineer Electrical
Gilbert, Arizona, United States
$98k-$148k/yr OnsiteFull Time
5+ YOEBachelor's in STEM +5 years (or Master's +3 / PhD +1) experience in RTL/HDL FPGA/ASIC design for aerospace/space, proficiency in FPGA design flow, verification, synthesis, timing and power analysis; strong communication and problem solving.
HDL, RTL, Xilinx ISE/Vivado, Mentor Graphics ModelSim/QuestaSim, Synplify, System Verilog, Universal Verification Methodology (UVM), Signal Generators, Logic Analyzers, Digital Oscilloscopes, Embedded FPGA Debugging tools
2w
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Aircraft Structural Dynamics Engineer
Wichita or Tucson or Opa-locka or Fort Worth or Windsor
OnsiteFull Time
15+ YOEUniversity engineering degree, 15+ years technical experience (10+ in aeronautics), 5+ years FPGA/ASIC or embedded software, knowledge of airborne software/hardware standards, DOORS/JAMA experience, C/C++/Ada95/Assembly/Python, OIQ membership preferred.
DOORS, JAMA, C, C++, Ada95, Assembly, Python
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