342 asic design engineer jobs at 61 companies in San Jose, CA
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ASIC Design Engineer
Santa Clara, California, United States
$127k-$190k/yr OnsiteFull Time
5+ YOE5+ years ASIC/SoC design and micro-architecture experience; expertise in RTL design, clocking, CDC/lint analysis, AMBA protocols; proficiency in Python and Perl; experience across full ASIC lifecycle.
Python, Perl, ARM CoreSight, AMBA, AHB, APB, AXI, PCIe, USB, FPGA, SoC
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Senior ASIC Design Engineer
Santa Clara, California, United States
$168k-$311k/yr OnsiteFull Time
8+ YOE8+ years RTL build/ASIC design, Verilog/SystemVerilog, ASIC flow knowledge, Bachelors/Masters in EE/CE.
Verilog, SystemVerilog, Digital Design, ASIC flow, timing analysis, RTL, ECO, Synthesis, Post-Silicon Debug
3d
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Senior ASIC Design Engineer
San Jose, California, United States
$168k-$245k/yr OnsiteFull Time
7+ YOEBachelor’s degree in Electrical or Computer Engineering plus 7+ years, master’s plus 4+ years, or PhD plus 1+ year of ASIC design experience; Verilog/SystemVerilog experience required.
Verilog, SystemVerilog, scripting
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Mid Level ASIC Design Engineer
Sunnyvale or Munich
OnsiteFull Time
3+ YOERequires 3+ years of ASIC RTL design experience with Verilog or SystemVerilog, CPU IP integration, processor architecture and interface knowledge, front-end ASIC tools, low-power design, and a bachelor's degree in electrical or computer engineering.
Verilog, SystemVerilog, ARM, RISC-V, MIPS, AMBA, APB, AXI, SPI, eMMC, MII, GPIO, I2C, UPF
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Senior ASIC Design Engineer
Santa Clara or California
$136k-$265k/yr HybridFull Time
5+ YOEBS/MS or equivalent,5+ years ASIC/SoC design experience,RTL design,logic synthesis,timing analysis,and strong scripting in Perl/Python/C++.
Perl, Python, C++, ARM
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ASIC Design Engineer
Cupertino, California, United States
OnsiteFull Time
Seeking a dedicated engineer with passion for innovation, problem solving, and hardware design to contribute to next-generation Apple products.
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ML ASIC Design Engineer
Mountain View or New York City
$175k-$215k/yr HybridFull Time
5+ YOEBS in Computer Engineering or equivalent experience; 5+ years with SystemVerilog, ASIC RTL design, and microarchitecture; 3+ years designing high-performance CPU, GPU, or NPU cores; Python or C++.
SystemVerilog, Python, C++, Chisel, Scala
2d
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ASIC & FPGA Design Engineer Stf - E4
Littleton or Sunnyvale or Denver or Boulder or Louisville or Highlands Ranch or King of Prussia
$136k-$252k/yr OnsiteFull Time
Bachelor of Science in Electrical Engineering or related field, or equivalent experience; ASIC/FPGA design, debugging, or verification experience; active Top Secret clearance and U.S. citizenship required.
ASIC, FPGA, Microsoft Project, Microsoft Office, Atlassian JIRA, Earned Value Management System (EVMS)
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Lead ASIC Design Engineer
San Jose, California, United States
$144k-$230k/yr OnsiteFull Time
12+ YOE12+ years ASIC/SoC digital design experience, BS/MS in EE/CE, expert SystemVerilog/Verilog, front-end EDA tool fluency, proven tape-out history, US work authorization, strong communication and mentoring skills.
SystemVerilog, Verilog, SDC, CDC, Design Compiler, Genus, PrimeTime, Tempus, Lint, SpyGlass, JasperGold CDC, Synopsys, Cadence, Python, Tcl, Perl
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ASIC Design Engineer
San Jose, California, United States
OnsiteFull Time
BS/MS/PhD in Electrical/Computer Engineering; proficiency in RTL design using Verilog/SystemVerilog, logic and micro-architecture, familiarity with AMBA/PCIe/NAND/DDR, scripting (Python/Perl/TCL), and Linux command-line.
Verilog, SystemVerilog, AMBA, PCIe, NAND, DDR, Python, Perl, TCL, Linux
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Principal Engineer, ASIC Design Verification
San Jose, California, United States
$190k-$240k/yr OnsiteFull Time
12+ YOEMS in Electrical or Computer Engineering; 12+ years ASIC/SoC verification experience; SystemVerilog and UVM expert; verification environment design; scripting for automation.
SystemVerilog, UVM, Scripting (Python, Perl, Tcl, Shell)
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Senior ASIC Design Engineer – Processor Subsystem
Saratoga, California, United States
$150k-$220k/yr OnsiteFull Time
7+ YOESenior ASIC/SoC design with processor subsystem integration and RTL expertise.
SystemVerilog, VHDL, AMBA (AHB, APB, AXI), Synopsys VCS, Cadence Xcelium, Mentor Questa
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ASIC Engineer, Physical Design
Sunnyvale or Austin
$178k-$250k/yr OnsiteFull Time
8+ YOEBachelor's degree (or equivalent) and 8+ years in ASIC physical design with end-to-end implementation, experience with industry EDA tools, static timing analysis and multi-corner closure at advanced nodes (7nm or below); scripting and low-power experience preferred.
Synopsys IC Compiler, Cadence Innovus, Primetime, Calibre, Python, Tcl
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Senior ASIC Physical Design Engineer
Sunnyvale, California, United States
$163k-$237k/yr OnsiteFull Time
7+ YOEBachelor's degree or equivalent,7+ years physical design experience, proficiency in Python/Tcl/Perl, experience with STA and Synopsys/Cadence PnR tools, ASIC backend flows and DFT knowledge.
Python, Tcl, Perl, Synopsys, Cadence, Static Timing Analysis (STA)
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ASIC Design Engineer (eInfochips)
Mountain View, California, United States
OnsiteFull Time
5+ YOE5+ years Verilog/SystemVerilog design; Fusion Compiler experience; scripting; PCIe and AXI interfaces; ARM Fabric IP; IPXACT; EDA tools.
Fusion Compiler, VCS, Questa CDC, Spyglass Lint, Design Compiler, Genus, UPF, Python, Tcl, Perl, Verilog, SystemVerilog, AXI, AMBA, IPXACT
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ASIC Digital Design, Sr Staff Engineer
Noida or Bangalore or San Jose
OnsiteFull Time
8+ YOEBSEE/MSEE with 8+ years ASIC digital design experience; expertise in UCIe/PCIe/DDR/CXL/USB, SystemVerilog/Verilog, synthesis, CDC, formal, STA, Fusion Compiler, Perforce, and scripting (Perl/Shell).
SystemVerilog, Verilog, Fusion Compiler, Perforce, Perl, Shell
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ASIC Design Engineer (Video Silicon IP) - Multimedia Lab
San Jose, California, United States
OnsiteFull Time
2+ YOEM.S./Ph.D. in EE/CE, 2+ years ASIC front-end RTL ownership, proficiency in SystemVerilog/Verilog or HLS, familiarity with UVM/DPI/C++, Python scripting, and VLSI design concepts.
SystemVerilog, Verilog, High level Synthesis (HLS), UVM, DPI, C++, Python, AXI, APB, EDA, GitHub Copilot, Claude, ChatGPT, FPGA
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ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna Labs
Cupertino or Austin
$157k-$213k/yr OnsiteFull Time
Bachelor's degree in electrical engineering or related field; ASIC design, debugging, and multi-level logic verification experience. SystemVerilog proficiency preferred; Python or Perl automation experience preferred.
SystemVerilog, Python, Perl, ARM, DSP, WiMAX, 802.11ad
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SR ASIC Design Engineer - Ethernet Switch & High-Speed I/O
Santa Clara, California, United States
$175k-$300k/yr OnsiteFull Time
BS or MS in Electrical/Computer Engineering; experience with ASIC/RTL design; knowledge of Ethernet, SerDes, and high-speed I/O; scripting (Perl/Python/Shell); experience with SystemVerilog/Verilog; VCS; strong communication and problem-solving skills.
VCS, SystemVerilog, Verilog, Perl, Python, Shell, RTL design, SerDes
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Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Irvine or Austin or Sunnyvale
$160k-$220k/yr OnsiteFull Time
5+ YOEBachelor’s degree in electrical engineering, computer engineering or computer science; 5+ years ASIC/physical design experience; strong EDA tool knowledge; scripting skills; ability to work extended hours.
EDA tools, Python, Csh/Bash/Shell, Perl, TCL, Makefile
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