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ASIC Design Engineer
Sunnyvale, California, United States
$120k-$243k/yr OnsiteFull Time
3+ YOEDesign engineer with strong Verilog/SystemVerilog, ASIC design, RTL timing and verification experience.
Verilog, SystemVerilog, RTL, EDA tools, Python, Perl
2mo
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ASIC Design Engineer
United States
RemoteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
0+ YOEBS or MS in Electrical Engineering or Computer Engineering; 0–2 years ASIC digital design; SystemVerilog/Verilog RTL; digital design fundamentals; cross-functional collaboration.
SystemVerilog, Verilog, RTL, Synthesis, Timing
3w
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ASIC Design Engineer
Santa Clara, California, United States
$127k-$190k/yr OnsiteFull Time
5+ YOE5+ years ASIC/SoC design and micro-architecture experience; expertise in RTL design, clocking, CDC/lint analysis, AMBA protocols; proficiency in Python and Perl; experience across full ASIC lifecycle.
Python, Perl, ARM CoreSight, AMBA, AHB, APB, AXI, PCIe, USB, FPGA, SoC
3mo
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ASIC Design Engineer
California or United States
OnsiteFull Time
10+ YOEBachelor's degree with 10+ years of experience in ASIC design and hardware architecture.
3mo
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ASIC Design Engineer
Sunnyvale, California, United States
$120k-$243k/yr OnsiteFull Time
3+ YOEDesign ASICs using Verilog/SystemVerilog; strong digital design, timing, RTL, verification, and collaboration with cross-functional teams.
Verilog, SystemVerilog, EDA tools, Synthesis, Lint, Perl, Python
2mo
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Sr. Engineer, ASIC Design
San Jose, California, United States
$160k-$192k/yr OnsiteFull Time
1+ YOEBS or MS in Electrical/Computer Engineering; 1+ years ASIC design; Verilog; ASIC verification tools; scripting; ability to work independently.
Verilog, Xcelium, VCS, Questa, Python, C, C++
3mo
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ASIC Design Engineer
Irvine or Andover
$108k-$173k/yr OnsiteFull Time
6+ YOEBachelor's in Electrical Engineering with 8+ years of related experience or Master's in Electrical Engineering with 6+ years of related experience; ASIC implementation, synthesis, DFT, floorplanning, place & route, clocking, power planning and analysis, timing closure, signal integrity, physical design checks.
EDA tools, Synthesis tools, Place and Route (P&R) tools, Floorplanning tools, Clocking/Timing analysis tools, Power analysis tools
1w
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Senior ASIC Design Engineer
Santa Clara or United States
$136k-$265k/yr HybridFull Time
5+ YOE5+ years ASIC or SoC design experience; BS/MS in relevant engineering or equivalent; RTL design, logic synthesis, timing analysis, SOC integration experience; strong scripting/programming (Perl, Python, C++).
Perl, Python, C++
2mo
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ASIC Design Engineer lll
Sunnyvale, California, United States
$120k-$243k/yr OnsiteFull Time
4+ YOEBachelor's in electrical engineering; 4+ years in ASIC/SoC design; strong Verilog/SystemVerilog; experience with EDA tools; good communication; Perl/Python a plus; AI tool experience a plus.
Verilog, SystemVerilog, EDA tools, Perl, Python
1w
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Senior ASIC Design Engineer
Santa Clara or California
$136k-$265k/yr HybridFull Time
5+ YOEBS/MS or equivalent,5+ years ASIC/SoC design experience,RTL design,logic synthesis,timing analysis,and strong scripting in Perl/Python/C++.
Perl, Python, C++, ARM
1mo
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Experienced Engineer - ASIC Design
Bangalore or Chennai or India or Sweden or United States
OnsiteFull Time
5+ YOEBachelors in electrical/computer engineering, 5+ years ASIC IP design experience, proficiency in SystemVerilog, RTL sign-off (SpyGlass), scripting (TCL, Python), AMBA (AXI, CHI), Cadence/Synopsys tool suites, and strong English communication.
SystemVerilog, SpyGlass, TCL, Python, AMBA, AXI, CHI, SystemVerilog Assertions, Cadence, Synopsys, Jenkins, Simscope, Jira, UPF
3mo
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Sr. ASIC Design Engineer (Starshield)
Hawthorne, California, United States
$160k-$225k/yr OnsiteFull Time
5+ YOEBachelor’s degree in electrical or computer engineering or computer science; 5+ years RTL/FPGA/ASIC experience.
Verilog, SystemVerilog, RTL, FPGA, ASIC, Python, TCL, EDA tools (HDL simulators: VCS, Questa, IES), Spyglass, Xilinx Vivado, Quartus II, AXI, AHB
1mo
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Senior Engineer - ASIC Design (786532)
Bengaluru or Chennai or Sweden or United States
OnsiteFull Time
10+ YOEBachelor's in electrical/computer engineering, 10+ years ASIC IP design, SystemVerilog, SpyGlass, synthesis/timing knowledge, TCL/Python scripting, AMBA (AXI/CHI), SVA; Cadence and Synopsys experience preferred.
SystemVerilog, SpyGlass, TCL, Python, AMBA, AXI, CHI, Cadence, Synopsys, MATLAB, UPF, Jenkins, Simscope, Jira
3mo
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ASIC/SoC Design Engineer
San Jose or United States
$146k-$250k/yr OnsiteFull Time
Experience in ASIC/SoC design, RTL/verification, Verilog/SystemVerilog, timing constraints, PD integration, DFT, and cross-domain collaboration.
Verilog, SystemVerilog, SystemVerilog Assertions, SDC timing constraints, ASIC CAD tools, AMBA AXI/AXI-S/APB, UPF, Perl, Python, Makefile
3w
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Senior ASIC Package Design Engineer
Los Angeles or United States
$180k-$260k/yr RemoteFull Time
5+ YOEBachelor's in engineering, 5+ years ASIC package design experience (FC-BGA), expertise in substrate technologies, SI/PI and thermal management, experience with OSATs and package qualification.
SIWave, HFSS, ADS
2d
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SR ASIC Design Verification Engineer
San Jose, California, United States
$165k-$241k/yr OnsiteFull Time
1+ YOEDegree in electrical/computer engineering or related plus multi-year ASIC verification experience; proficiency in System Verilog and UVM; ASIC verification, simulation, emulation, post-silicon debug experience; Linux and programming (C/C++, Python/Perl).
System Verilog, UVM, Veloce, Palladium, Zebu, HAPS, Linux, C/C++, Python/Perl
1mo
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ASIC/FPGA Design Engineer IV
Littleton or California or Massachusetts or New York or Colorado or Hawaii or Illinois or Maryland or Minnesota or New Jersey or Vermont or Washington or District of Columbia
$124k-$218k/yr OnsiteFull Time
5+ YOEUS citizen able to obtain and maintain DoD Secret clearance, BS in Computer/Electrical Engineering or equivalent, 5+ years professional experience, HDL experience (VHDL/Verilog/SystemVerilog), ASIC/FPGA design and verification experience, Linux proficiency.
VHDL, Verilog, SystemVerilog, Linux, Microsoft Project, Microsoft Office, Atlassian JIRA, Earned Value Management System (EVMS)
2mo
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Senior ASIC Design Engineer – Processor Subsystem
Saratoga, California, United States
$150k-$220k/yr OnsiteFull Time
7+ YOESenior ASIC/SoC design with processor subsystem integration and RTL expertise.
SystemVerilog, VHDL, AMBA (AHB, APB, AXI), Synopsys VCS, Cadence Xcelium, Mentor Questa
2mo
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ASIC Digital Design Engineer-17369
Boxborough or Markham or Mississauga or Ottawa
$138k-$208k/yr OnsiteFull Time
Experienced ASIC digital designer/verifier with Verilog, Perl, Tcl, and Python skills; knowledge of RTL design/verification, static timing analysis, synthesis, simulation, and debugging; HBM/DDR protocol experience preferred.
Verilog, Perl, Tcl, Python
1mo
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Principal Engineer - FPGA/ASIC Design
Indianapolis or West Lafayette
$113k-$184k/yr HybridFull Time
3+ YOEU.S. citizen with degree in electronics/computer engineering and 3+ years experience (or higher degree), expertise in FPGA/ASIC design (VHDL/Verilog/SystemVerilog), DO-254 verification, timing closure, synthesis, testbenches, lab validation, and scripting (TCL/Python/Shell).
VHDL, Verilog, SystemVerilog, DO-254, TCL, Python, Shell, Windows, Linux, Git, SVN, Actel, Xilinx, MATLAB, Simulink, Cameo Systems Modeler (MagicDraw), ILA, JTAG, oscilloscopes, logic analyzers
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