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Principal ASIC Design Engineer - Terawave
San Diego or Kent or Austin or California
$269k-$377k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
10+ YOEBS/MS in Electrical Engineering or related,10+ years experience in complex SoC/ASIC design and verification,Verilog/System Verilog,ARM integration,DSP and high-speed interfaces,post-silicon bring-up experience.
Verilog, System Verilog, Matlab, SystemC, C, FPGA, AXI, PCIE, ARM
1mo
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Senior ASIC Design Verification Engineer
Seattle, Washington, United States
$170k-$250k/yr OnsiteFull Time
5+ YOEB.S./M.S. in EE/CE or related, 5+ years ASIC/SoC verification experience, strong SystemVerilog/UVM skills, simulation and waveform debug tool experience, scripting (Python/Perl/TCL), and familiarity with industry interfaces and CI/CD.
SystemVerilog, UVM, SystemVerilog Assertions (SVA), VCS, Xcelium, Questa, Verdi, SimVision, Python, Perl, TCL, Git, APB, AHB, AXI, C, C++, CI/CD
1mo
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Manager, ASIC Sustaining engineer, Silicon Operations
Sunnyvale or Bellevue or San Diego
$175k-$272k/yr OnsiteFull Time
5+ YOE5+ Mgmt5+ years technical program management and people management experience; Bachelors in engineering/CS; experience with Unix/Linux, yield improvement, root cause and failure analysis, DOE, and partnering with process/equipment/design teams.
Unix, Linux, AWS, Agile
1mo
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ASIC Engineering Technical Leader - CDC
San Jose or Austin or Seattle
$184k-$264k/yr HybridFull Time
8+ YOEExpertise in RTL development, CDC/RDC methodology, and static glitch analysis; 6–8+ years related experience (varies by degree); experience maintaining CDC/RDC flows and signing off constraints and waivers.
RTL, SDC, VCS, SystemVerilog Assertions (SVA)
2mo
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FPGA/ASIC Design Engineer (Silicon Engineering)
Irvine or Redmond
$125k-$145k/yr OnsiteFull Time
1+ YOEBachelor’s in EE/CE/CS/Physics; 1+ years RTL design (SystemVerilog/Verilog/VHDL); strong Python/C/C++, and PCB/lab experience.
Verilog/SystemVerilog, VHDL, Python, C/C++, Bash, HDL simulators, Spyglass, Vivado, Quartus, AXI/APB/AHB protocols
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Electrical Engineer II
Lynnwood, Washington, United States
$102k-$119k/yr OnsiteFull Time
3+ YOEBA/BS in engineering, 3+ years relevant experience, knowledge of analog/digital/micro-electronics, VHDL, power and ASIC design, and experience with testing and product development.
VHDL
2mo
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Senior Digital Design Engineer
Santa Clara or Austin or Redmond
$136k-$265k/yr OnsiteFull Time
5+ YOE5+ years experience in digital/ASIC design, degree in EE/CE or equivalent, experience with high-speed protocols (NVLink, PCI-Express, Ethernet, UCIE), RTL implementation, and ASIC design flows.
NVLink, PCI-Express, Ethernet, UCIE, RTL
2mo
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Senior Electrical Engineer, Radiation Effects & Avionics Reliability
Seattle, Washington, United States
$150k-$200k/yr OnsiteFull Time
4+ YOEBachelor’s in Electrical Engineering; 4+ years in radiation effects, avionics reliability, or high-reliability electronics; hands-on radiation testing; experience with FMEA/FMECA, FTA, derating; knowledge of FPGA/ASIC/power systems; able to translate test data into design decisions.
FPGAs, ASICs, Power electronics, COTS, Radiation test equipment, SPENVIS, OMERE, NOVICE
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Senior Silicon Design Engineer
Redmond or Mountain View
$120k-$235k/yr HybridFull Time
Degree in EE/CE/CS (or equivalent experience) with multi-year ASIC/SoC/IP design experience, RTL/Verilog/SystemVerilog skills, CDC/Lint/synthesis experience, scripting (Perl/Python) and ability to pass export-control and background screenings.
Verilog/System Verilog, Perl, Python, AXI, APB, JTAG, SDC, UPF
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Cloud Acceleration Engineer – DPU & AI Infra
Seattle, Washington, United States
OnsiteFull Time
2+ YOE2+ years industry experience (PhD exception), proficiency in C/C++ and Linux systems, strong understanding of compute/network architecture and OS, experience in software-hardware co-design or high-performance networking or AI/ML systems.
C/C++, Linux, OVS, SR-IOV, eBPF, DPDK, FPGA, ASIC, GPU, CUDA, NCCL
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