86 asic engineer jobs at 21 companies in Cudahy, CA
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Principal Engineer ASIC or Sr Principal Engineer ASIC
Manhattan Beach, California, United States
$125k-$235k/yr OnsiteFull Time
5+ YOESTEM degree with relevant years of experience, RTL design (VHDL/Verilog/SystemVerilog), ASIC/FPGA architecture, verification experience, lab testing, and ability to obtain a government security clearance.
VHDL, Verilog, SystemVerilog, Xilinx Vivado, Microchip Libero, UVM
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Principal Engineer ASIC or Sr Principal Engineer ASIC
Manhattan Beach, California, United States
$125k-$235k/yr OnsiteFull Time
5+ YOESTEM degree with 3–8+ years experience, RTL design (VHDL/Verilog) for space, ASIC/FPGA architecture, verification (SystemVerilog/UVM), lab testing, and ability to obtain/maintain government security clearance.
VHDL, Verilog, Xilinx Vivado, Microchip Libero, SystemVerilog, UVM, DSP
2mo
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Sr. ASIC DFT Engineer (Silicon)
Irvine or Austin or Sunnyvale
$125k-$150k/yr OnsiteFull Time
5+ YOEBachelor's in engineering or physics; 5+ years in DFT/semiconductor testing; strong ASIC/DFT/ATE expertise.
Siemens Tessent, ATPG, Teradyne, Advantest, Perl, Python, Tcl, C++, IEEE 1500, IEEE 1687, IST
2w
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Senior ASIC Emulation Engineer
Los Angeles or United States
$170k-$250k/yr OnsiteFull Time
5+ YOE5+ years ASIC/SoC emulation experience, SystemVerilog and RTL knowledge, hands-on with Palladium/ZeBu/Veloce, scripting (Python/Perl/TCL), C/C++ firmware experience, and cross-functional debug skills.
Palladium, ZeBu, Veloce, SystemVerilog, Python, Perl, TCL, C, C++, APB, AHB, AXI, JTAG, SPI, HAPS, Protium, PCIe, Ethernet, USB, SERDES
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ASIC Verification Engineer
Irvine or San Jose
$101k-$162k/yr OnsiteFull Time
3+ YOEEngineering degree (Bachelors/Masters/PhD) with 3+ years verification experience (varies by degree), proficiency in HDL and verification, C/C++, scripting, strong communication and teamwork.
SystemVerilog UVM, SystemVerilog, Verilog, VHDL, C, C++, Python, PERL, TCL
1d
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ASIC / FPGA Digital Design Engineer – (Lead or Senior)
El Segundo or Huntington Beach
$146k-$223k/yr OnsiteFull Time
9+ YOEBachelor's degree in a related technical field and 9+ years of FPGA, ASIC, or SoC digital design experience; HDL, simulation, synthesis, troubleshooting, timing, and CDC knowledge required.
ASIC, FPGA, SoC, HDL, RTL
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ASIC / FPGA Digital Design Engineer – (Lead or Senior)
El Segundo or Huntington Beach
$146k-$223k/yr OnsiteFull Time
7+ YOEBachelor's degree in a related technical field and 7–9+ years of ASIC, FPGA, or SoC digital design experience; HDL development, simulation, synthesis, troubleshooting, timing, and CDC knowledge required.
HDL, RTL, ASIC, FPGA, SoC
2mo
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Senior ASIC Design Verification Engineer - Terawave
Los Angeles or Seattle or California or Washington or Texas or United States
$230k-$323k/yr RemoteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
8+ YOEBS/MS in EE/CE, 8+ years ASIC/SoC verification experience, deep System Verilog and UVM expertise, verification planning, coverage closure, RTL/debugging, cross-functional collaboration.
System Verilog, UVM, RTL
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ASIC Engineer, Physical Design Engineer
Aliso Viejo, California, United States
OnsiteFull Time
5+ YOERequires 5+ years of experience, physical design and timing closure expertise, EDA tool experience, floorplanning, place and route, power and clock distribution, timing convergence, and U.S. citizenship.
Perl, Tcl, Innovus, ICC2, PrimeTime, RedHawk, Voltus, Calibre, EDA
2mo
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Senior ASIC/FPGA Verification Engineer (Onsite)
El Segundo or Fullerton
$96k-$182k/yr OnsiteFull Time
5+ YOEActive transferable U.S. SECRET clearance and U.S. citizenship, STEM degree (BS or advanced) with 5+ years (BS) or 3+ years (advanced) experience, RTL verification using VHDL/Verilog/SystemVerilog, testbench and coverage, and revision control (Git/Subversion).
SystemVerilog, OVM, UVM, VHDL, Verilog, Git, Subversion, QuestaSim, Synplify, Quartus, Vivado, Unix, Linux
1mo
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Sr. ASIC Design Verification Engineer, Amazon Leo
Sunnyvale or San Diego or Los Angeles County
$159k-$248k/yr OnsiteFull Time
7+ YOEBachelor's in CS/CE/EE, 7+ years verification experience (communications preferred), 5+ years with UVM and C/C++ and scripting, familiarity with Matlab and formal verification preferred; must meet U.S. export-control eligibility.
UVM, SystemC, DPI-C, Matlab, C/C++, FPGA
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Senior ASIC Chip Lead / Project Lead (TERADYNE, Agoura Hills, CA)
Agoura Hills, California, United States
$192k-$308k/yr OnsiteFull Time
15+ YOE5+ MgmtBSEE, MSEE, or equivalent; 15+ years of semiconductor experience; 5+ years leading complex ASIC development; mixed-signal ASIC delivery, distributed teams, external partners, program management, risk management, and executive communication.
ASIC, ATE, EDA
2mo
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Senior Principal Engineer, Architecture ASIC / System
Toronto or Ottawa or Burlington or Irvine or Morrisville or Santa Clara or Westborough
$192k-$255k/yr OnsiteFull Time
14+ YOESenior architect with 14+ years in system architecture for SoC; expertise in interconnects, memory hierarchies, power management, security; strong technical leadership.
IP evaluation, IP block, SoC architecture
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Hardware Engineer
Colorado Springs or Irvine or Longmont or Fremont or Rochester or San Jose
$91k-$113k/yr OnsiteFull Time
Early-career candidates pursuing or recently completing an engineering degree; familiarity with hardware, firmware, ASIC/SoC, or systems; programming and design experience through coursework or projects; strong analytical and communication skills.
Verilog/SystemVerilog, RTL, FPGA, C, C++, Assembly, Python, Java, Go, SQL, JavaScript, Git, Linux, IDE, CAD, Microsoft Office, RTOS
2mo
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Hardware Engineer, Mid
El Segundo, California, United States
$62k-$141k/yr OnsiteFull Time
7+ YOE7+ years hardware engineering experience, bachelor’s in Electrical or Computer Engineering, Secret clearance, experience with avionics hardware reviews (PDR/CDR/TRR), requirements and verification development, risk management, and up to 10% travel.
VHDL, Verilog, embedded C, ASIC, FPGA, DO-254
2mo
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Electrical Engineer III/IV
Burbank, California, United States
$125k-$177k/yr OnsiteFull Time
8+ YOEBA/BS in engineering, 8+ years relevant experience, US Person required for ITAR work, expertise in analog/digital/micro-electronics, VHDL, ASIC, DO-254/DO-160, magnetics, switching power supplies, hardware/software integration, and strong communication skills.
VHDL, DO-254, DO-160, Kaizen, 5S, Lean
1d
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FPGA Verification Engineer, Air Dominance and Strike
Costa Mesa, California, United States
$146k-$194k/yr OnsiteFull Time
2+ YOEBachelor’s degree in electrical or computer engineering, 2+ years of FPGA/ASIC verification experience, SystemVerilog, UVM, SVA, simulators, Git, Linux, and eligibility for a U.S. Secret clearance.
SystemVerilog, UVM, SystemVerilog Assertions (SVA), Questa, VCS, Xcelium, Vivado, Git, Linux, SVUnit, Python, Tcl, Makefile, Ethernet, PCIe, JESD204C, MIL-STD-1553, SPI, CI/CD, Nix, ARM
1mo
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Digital Design Principal Engineer/Manager
Irvine, California, United States
$190k-$225k/yr OnsiteFull Time
20+ YOE20+ years FPGA/SoC development with leadership experience; MS in Electrical Engineering; deep Verilog/SystemVerilog expertise; FPGA/ASIC implementation and packet processing experience; scripting in C/C++, Perl, Tcl, Python.
Verilog, SystemVerilog, AMD (Xilinx Vivado), C, C++, Perl, Tcl, Python, Claude Code, Copilot
4d
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Principal Physical Design Engineer
San Jose or Irvine
$150k-$250k/yr OnsiteFull Time
5+ YOE5+ years of ASIC physical design experience, advanced-node tapeout expertise, EDA tool proficiency, and expertise in synthesis, power analysis, EM/IR cleanup, timing closure, and physical verification.
System-on-Chips (SoCs), RTL, GDSII, Static Timing Analysis (STA), Design Rule Checking (DRC), Layout Versus Schematic (LVS), Tcl, Python, Perl, Cadence Innovus, Cadence Tempus, Cadence Voltus, Cadence Pegasus, Calibre
1mo
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Senior Principal Digital Design Engineer
Irvine, California, United States
$186k-$228k/yr OnsiteFull Time
6+ YOEExpert digital ASIC design experience, SystemVerilog/RTL implementation, block/system verification, synthesis/power/timing analysis, and technical leadership; BS in EE (or advanced) plus extensive experience.
SystemVerilog, Verilog, UVM, SystemC, PCIe, PCI-SIG, IEEE 802.3, SDC
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