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Sr. ASIC Design Engineer, Blink/Ring ASIC Team
North Reading, Massachusetts, United States
$159k-$215k/yr OnsiteFull Time
Bachelor's in Electrical Engineering, knowledge of UVM and Matlab, experience delivering products to volume production, low-power design expertise, RTL coding and debug, and leadership in technical initiatives.
UVM, Matlab, RTL
1mo
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ASIC Design Verification Engineer
Irvine or Andover or Broomfield
$129k-$207k/yr OnsiteFull Time
3+ YOEConstrained-random design verification experience using System Verilog/UVM, coverage-driven methodologies, experience with VCS/Incisive and scripting (Python/Perl). Degree with significant related experience required (varies by degree).
System Verilog, UVM, VCS, Incisive, Python, Perl
2mo
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ASIC & FPGA Design Engineer Senior Staff
Andover or Chelmsford
$145k-$289k/yr OnsiteFull Time
Bachelor's in EE (or equivalent), HDL experience (VHDL/Verilog/SystemVerilog), FPGA toolchain experience (Vivado/Quartus), FPGA simulation/verification (UVM, Synopsys VCS, SystemC), Git/GitLab, ability to obtain Secret clearance and U.S. citizenship required.
VHDL, Verilog, SystemVerilog, Xilinx Vivado, Intel Quartus, UVM, SystemC, Python, Synopsys VCS, GitLab, Git, C, C++, Altera, Microchip, Xilinx
1mo
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Principal Digital Design Engineer (ASIC)
Somerset or Wilmington
$160k-$239k/yr OnsiteFull Time
10+ YOE10+ years ASIC/SoC digital design experience, Bachelor’s degree in EE/CE, expertise in SystemVerilog/Verilog, RTL design, synthesis, timing closure, MATLAB/TCL/Python modeling, Cadence tools, and tapeout experience.
SystemVerilog, MATLAB, Verilog, Python, TCL, Cadence, UVM
1mo
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Senior Electrical Engineer
Wilmington, Massachusetts, United States
$115k-$173k/yr OnsiteFull Time
5+ YOEBS/MS in Electrical Engineering, 5+ years product development experience, motion control required, embedded microprocessors, PCB layout (Altium) experience, firmware/FPGA/Verilog knowledge, ability to support system-level design and testing.
PCB Layout Tools, Altium, PLD, FPGA, ASIC, Verilog
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Principal FPGA Digital Design Engineer - Sign-on Bonus
Nashua, New Hampshire, United States
OnsiteFull Time
6+ YOESecret-clearable engineer with 6+ years FPGA/ASIC experience, VHDL/Verilog RTL coding, timing closure, lab debug, familiarity with high-speed interfaces and revision control.
VHDL, Verilog, Xilinx Vivado, Intel/Altera Quartus, ChipScope, SignalTap, ILA, Modelsim, Questa, GIT, CVS, Clearcase, Subversion, Perl, Tcl, Python, shell, Matlab, Simulink, UVM, SystemVerilog, C, C++
2mo
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FPGA Design Engineer
Nashua or Manchester or New Hampshire or United States
$97k-$165k/yr OnsiteFull Time
4+ YOEEligible for Secret clearance; typically a Bachelor's + 4+ years (or equivalent). FPGA/ASIC design experience with VHDL/Verilog, testbench development, timing closure, revision control, lab testing, and strong communication/problem-solving skills.
VHDL, Verilog HDL, SystemVerilog, UVM, GIT, CVS, Clearcase, Subversion, Xilinx Vivado, Intel/Altera Quartus, ModelSim, QuestaSim, MATLAB/Simulink, Perl, Tcl, Python, shell, C/C++, ILA, ChipScope, SignalTap
1mo
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Senior Electrical Engineer - FPGA Design
Tewksbury or Marlborough
$87k-$165k/yr OnsiteFull Time
5+ YOEU.S. citizen able to obtain/maintain Secret clearance; STEM bachelor's degree typically required; minimum 5 years relevant FPGA/ASIC design or verification experience with VHDL/Verilog/SystemVerilog; experience with Xilinx or Microsemi devices and integration/debug.
VHDL, Verilog, SystemVerilog, UVM, Xilinx, Microsemi, Veloce, ARM, MicroBlaze, Nios
1mo
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Principal Engineer Pre-Silicon Digital Verification
Andover or Austin or El Segundo
$146k-$201k/yr HybridFull Time
Experience in ASIC design and digital/mixed-signal verification, test plan and testbench development, SystemVerilog/UVM, RTL and functional coverage, formal verification, and scripting (Unix/Linux shell, Perl, Python).
SystemVerilog, UVM, Unix/Linux shell, Perl, Python
1mo
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Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)
San Diego or Nashua or Austin or Totowa or California or New Hampshire or Texas or New Jersey or United States
$130k-$222k/yr OnsiteFull Time
8+ YOEBachelor's degree with 8+ years (or equivalent experience); eligible for Secret clearance; experience with SystemVerilog/UVM/OVM and/or VHDL, Mentor Questa or Cadence tools; FPGA/ASIC verification, test plan development, and strong communication.
SystemVerilog, UVM, OVM, VHDL, Mentor Questa, Cadence, Perl, Python, C++, Java, Git, Jira, BitBucket, Matlab, Simulink
1mo
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Principal Engineer Pre-Silicon Digital Verification
Andover or Austin or El Segundo
$146k-$201k/yr OnsiteFull Time
Expertise in ASIC design and digital/mixed-signal verification, System Verilog and UVM, scripting (Unix/Linux shell, Perl, Python), testbench and coverage development, formal verification and analog behavioral modeling.
System Verilog, UVM, Unix/Linux shell, Perl, Python
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