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Senior ASIC Verification Engineer
Durham or Madison or Hillsboro
$136k-$265k/yr OnsiteFull Time
5+ YOEBachelor's or Master's in EE/CS/CE (or equivalent), 5+ years ASIC verification experience, strong SystemVerilog and C/C++ skills, UVM, constrained-random and coverage-driven verification, familiarity with VCS/IES and debug tools.
SystemVerilog, C, C++, Universal Verification Methodology (UVM), VCS, IES, Debussy, GDB, Semiformal Verification (SFV), Perl, Python
3mo
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ASIC Design Engineer
Beaverton, Oregon, United States
OnsiteFull Time
10+ YOEBS and 10+ years of relevant industry experience; Verilog RTL design experience.
Verilog, RTL, Synthesis, EDA, Front end tools
1mo
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Senior ASIC Verification Engineer
Durham or Madison or Hillsboro
$136k-$265k/yr OnsiteFull Time
5+ YOEBachelors/Masters in EE/CS/CE or equivalent, 5+ years verification experience, strong SystemVerilog and C/C++ skills, verification methodology experience (UVM, constrained-random, coverage, assertions), familiarity with VCS/IES and debug tools.
SystemVerilog, C, C++, VCS, IES, Debussy, GDB, Universal Verification Methodology (UVM), Semiformal Verification (SFV), Perl, Python
4d
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ASIC Layout Designer
Boulder or Louisville or Beaverton
OnsiteFull Time
7+ YOEMinimum 7 years RF/analog/mixed-signal layout experience; proficient in broadband RF/high-speed layout, PDKs, floor planning, parasitic minimization, physical verification, and mentoring teams.
Cadence Virtuoso Schematic L, Layout L, Layout XL, Cadence Assura, PVS, Pegasus, Calibre, customIC, Solido, Aprisa, Questa, SVN, SOS, Synchronicity, IC Manage, Skill, Python, Ruby, Shell, Cadence Allegro PCB Design
4d
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ASIC Layout Designer
Boulder or Beaverton
$104k-$192k/yr OnsiteFull Time
7+ YOE7+ years RF/analog/mixed-signal layout experience; proficiency with PDKs, broadband RF/high-speed layout, parasitic minimization, floor planning, verification, and mentoring; scripting (Skill, Python, Ruby, Shell).
Cadence Virtuoso Schematic L, Cadence Virtuoso Layout L, Cadence Virtuoso Layout XL, Cadence Assura, PVS, Pegasus, Calibre, customIC, Solido, Aprisa, Questa, SVN, SOS, Synchronicity, IC Manage, Skill, Python, Ruby, Shell scripting, Cadence Allegro PCB Design
3mo
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Hardware Design Engineer
Hillsboro, Oregon, United States
$107k-$199k/yr HybridFull Time
5+ YOEStrong SystemVerilog/Verilog RTL design, ASIC/FPGA experience, RTL verification, scripting, 5+ years, BSEE.
SystemVerilog, Verilog, Questa, Incisive, VCS, Python, Perl, Tcl
1mo
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Principal Silicon Design Verification Engineer
Santa Clara or Mountain View or Hillsboro or Austin or Redmond
$143k-$275k/yr HybridFull Time
3+ YOEDegree in EE/CE/CS (or equivalent) with 3+ to 8+ years technical engineering experience depending on degree, experience in ASIC/SoC verification, UVM/SystemVerilog/Verilog and C proficiency, ability to pass Microsoft security screening.
UVM, C, Verilog, System Verilog
2mo
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Senior Applications and Solutions Engineer - Foundry Services
Phoenix or Santa Clara or Hillsboro
$122k-$232k/yr HybridFull Time
4+ YOEUS citizen; ability to obtain US government security clearance; 4+ years CMOS/low-power/multi-voltage domain; ASIC design and verification experience; scripting in Python/Perl/Tcl.
Cadence, Synopsys, UPF/CPF, VCLP, Conformal LP, Python, Perl, Tcl
1mo
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Field Applications Engineering
San Jose or Hillsboro
OnsiteFull Time
7+ YOE7+ years FPGA/ASIC design experience with VHDL/Verilog/SystemVerilog and tool experience (Radiant, Diamond, Quartus, Vivado); Bachelor's in Electrical Engineering; strong communication and presentation skills; customer-facing experience and periodic travel availability.
VHDL, Verilog, SystemVerilog, Radiant, Diamond, Quartus, Vivado
2w
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Applications Engineer - FPGA Prototyping
San Diego or Austin or Boulder or Costa Mesa or Pasadena or Tempe or Wilsonville or Fremont
$167k-$334k/yr HybridFull Time
5+ YOE5+ years in design/verification/FPGA/ASIC or similar; BS/MS in EE/CE/CS; active experience with SystemVerilog/Verilog/VHDL, FPGA tools, scripting, simulation and customer-facing technical support.
SystemVerilog, Verilog, VHDL, SystemC, C/C++, Perl, Python, XML, JSON, proFPGA, HAPS, Xilinx Vivado, Altera Quartus, Questa, Incisive, VCS, OVM, UVM
1mo
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Principal Engineer - Memory-Centric AI Compute Architect
Hillsboro, Oregon, United States
$192k-$288k/yr OnsiteFull Time
6+ YOEMaster's/PhD preferred; 6+ years (PhD) / 7+ years (Master's) / 8+ years (Bachelor's) ASIC design/verification/validation/integration experience; knowledge of memory and compute architectures, AI models, and performance modeling; proficiency in C/C++/Python/Perl.
Phyton, C, C++, Perl, Python, HBM, DRAM
1w
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FPGA Engineering Manager (Nextest, Tualatin, OR)
Tualatin, Oregon, United States
$171k-$274k/yr OnsiteFull Time
12+ YOE5+ MgmtB.S./M.S. in EE,12+ years digital ASIC/FPGA design,5+ years project lead,verilog/RTL,Cadence and static timing tools,PCIe/DDR/AXI/SERDES experience,excellent communication and presentation skills.
verilog, RTL, Cadence, Vivado, Quartus, UVM, Linux, Windows, PCIe, DDR3, DDR4, DDR5, AXI, Ethernet, SPI, SERDES, Lint, CDC, ATE
3w
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Technical Director - Digital IC Design
San Jose or Hillsboro
$170k-$340k/yr OnsiteFull Time
12+ YOEBachelor's in EE/CE required (Master's/PhD preferred), 12+ years in digital IC design with hardware DSP focus, proven ASIC/SoC delivery, team leadership, RTL (Verilog/SystemVerilog/SystemC), synthesis/timing/simulation, FPGA prototyping, low-power and physical design expertise.
Verilog, SystemVerilog, SystemC, JasperGold
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