3mo
Save
Mark Applied
Hide
RTL Design Engineer
Beaverton, Oregon, United States
OnsiteFull Time
Bachelor's degree in Electrical Engineering; experience with RTL design and Verilog/SystemVerilog preferred.
Verilog, SystemVerilog, Python, Perl
3mo
Save
Mark Applied
Hide
RTL Design Engineer
Austin or Phoenix or Hillsboro
$106k-$200k/yr OnsiteFull Time
2+ YOEBachelor’s or Master’s in Electrical/Computer Engineering with 2+ years experience; knowledge of RTL design, Verilog/SystemVerilog, and basic digital design.
Verilog, SystemVerilog, VHDL, Design Compiler, Genus, Python, Perl, TCL, ModelSim, VCS, Xcelium, UVM, OVM
2mo
Save
Mark Applied
Hide
Principal PCIe CXL RTL Design Engineer
Aix-en-Provence or Sofia or Hillsboro or Bangalore
HybridFull Time
5+ YOE5+ years RTL design experience; expertise in Verilog/System Verilog; Master’s degree or PhD in Electrical or Computer Engineering (or equivalent); knowledge of PCIe/CXL/AMBA; FPGA prototyping; strong English and collaboration skills.
System Verilog, Verilog, PCIe, CXL, AMBA, FPGAs
3d
Save
Mark Applied
Hide
Senior Silicon Engineer
Redmond or Austin or Raleigh or Hillsboro
$120k-$235k/yr HybridFull Time
1+ YOEDegree in EE/CE/CS or equivalent with 1–5+ years technical engineering experience depending on degree; expertise in RTL, synthesis, STA, PD flows; proficiency in Tcl and Python; ability to pass Microsoft cloud background and export-control screenings.
PrimeTime, Genus, DC, Innovus, ICC2, Tcl, Python
1w
Save
Mark Applied
Hide
CPU Design Methodology Engineer
Hillsboro or Austin or Santa Clara or Arizona
$136k-$265k/yr OnsiteFull Time
5+ YOEMasters in Computer or Electrical Engineering or equivalent,5+ years chip/SOC design experience,RTL/verification and design automation expertise,proficient in scripting (Perl/Python),strong analytical and interpersonal skills.
Verilog, UVM, System Verilog, Perl, Python
1w
Save
Mark Applied
Hide
MTS Logic Design
Hillsboro, Oregon, United States
$86k-$160k/yr HybridFull Time
Bachelor's degree in engineering, knowledge of Verilog/System Verilog, RTL design and verification, strong communication skills.
Verilog, System Verilog, RTL
1w
Save
Mark Applied
Hide
CPU Design Methodology Engineer
Hillsboro or Austin or Santa Clara or United States
$136k-$265k/yr HybridFull Time
5+ YOEMasters in Computer/Electrical Engineering or equivalent experience,5+ years chip/SOC design experience,RTL (Verilog),UVM/System Verilog,design automation,Perl/Python skills,analytical and interpersonal skills.
Verilog, UVM, System Verilog, Perl, Python
2w
Save
Mark Applied
Hide
Senior FPGA Design Engineer (Nextest, Tualatin, OR)
Tualatin or San Jose
$170k-$273k/yr OnsiteFull Time
8+ YOEB.S. or M.S. in electrical engineering,8+ years relevant experience,RTL/Verilog,Intel/Xilinx tool flows,static timing analysis,FPGA transceivers,EM simulation lab validation,C/C++,Linux/Windows proficiency.
C, C++, Verilog HDL, Intel/Xilinx FPGA tool flows, UVM, Linux, Windows, oscilloscope, power supply, waveform generator, ATE
4w
Save
Mark Applied
Hide
Technical Director - Digital IC Design
San Jose or Hillsboro
$170k-$340k/yr OnsiteFull Time
12+ YOEBachelor's in EE/CE required (Master's/PhD preferred), 12+ years in digital IC design with hardware DSP focus, proven ASIC/SoC delivery, team leadership, RTL (Verilog/SystemVerilog/SystemC), synthesis/timing/simulation, FPGA prototyping, low-power and physical design expertise.
Verilog, SystemVerilog, SystemC, JasperGold
Explore Jobs