71 asic engineer jobs at 20 companies in Ladera Ranch, CA
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Principal Engineer ASIC or Sr Principal Engineer ASIC
Manhattan Beach, California, United States
$125k-$235k/yr OnsiteFull Time
5+ YOESTEM degree with 3–8+ years experience, RTL design (VHDL/Verilog) for space, ASIC/FPGA architecture, verification (SystemVerilog/UVM), lab testing, and ability to obtain/maintain government security clearance.
VHDL, Verilog, Xilinx Vivado, Microchip Libero, SystemVerilog, UVM, DSP
2mo
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Sr. ASIC DFT Engineer (Silicon)
Irvine or Austin or Sunnyvale
$125k-$150k/yr OnsiteFull Time
5+ YOEBachelor's in engineering or physics; 5+ years in DFT/semiconductor testing; strong ASIC/DFT/ATE expertise.
Siemens Tessent, ATPG, Teradyne, Advantest, Perl, Python, Tcl, C++, IEEE 1500, IEEE 1687, IST
2w
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Senior ASIC Emulation Engineer
Los Angeles or United States
$170k-$250k/yr OnsiteFull Time
5+ YOE5+ years ASIC/SoC emulation experience, SystemVerilog and RTL knowledge, hands-on with Palladium/ZeBu/Veloce, scripting (Python/Perl/TCL), C/C++ firmware experience, and cross-functional debug skills.
Palladium, ZeBu, Veloce, SystemVerilog, Python, Perl, TCL, C, C++, APB, AHB, AXI, JTAG, SPI, HAPS, Protium, PCIe, Ethernet, USB, SERDES
3w
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ASIC Verification Engineer
Irvine or San Jose
$101k-$162k/yr OnsiteFull Time
3+ YOEEngineering degree (Bachelors/Masters/PhD) with 3+ years verification experience (varies by degree), proficiency in HDL and verification, C/C++, scripting, strong communication and teamwork.
SystemVerilog UVM, SystemVerilog, Verilog, VHDL, C, C++, Python, PERL, TCL
1d
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ASIC / FPGA Digital Design Engineer – (Lead or Senior)
El Segundo or Huntington Beach
$146k-$223k/yr OnsiteFull Time
9+ YOEBachelor's degree in a related technical field and 9+ years of FPGA, ASIC, or SoC digital design experience; HDL, simulation, synthesis, troubleshooting, timing, and CDC knowledge required.
ASIC, FPGA, SoC, HDL, RTL
1d
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ASIC / FPGA Digital Design Engineer – (Lead or Senior)
El Segundo or Huntington Beach
$146k-$223k/yr OnsiteFull Time
7+ YOEBachelor's degree in a related technical field and 7–9+ years of ASIC, FPGA, or SoC digital design experience; HDL development, simulation, synthesis, troubleshooting, timing, and CDC knowledge required.
HDL, RTL, ASIC, FPGA, SoC
2mo
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Senior ASIC Design Verification Engineer - Terawave
Los Angeles or Seattle or California or Washington or Texas or United States
$230k-$323k/yr RemoteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
8+ YOEBS/MS in EE/CE, 8+ years ASIC/SoC verification experience, deep System Verilog and UVM expertise, verification planning, coverage closure, RTL/debugging, cross-functional collaboration.
System Verilog, UVM, RTL
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ASIC Engineer, Physical Design Engineer
Aliso Viejo, California, United States
OnsiteFull Time
5+ YOERequires 5+ years of experience, physical design and timing closure expertise, EDA tool experience, floorplanning, place and route, power and clock distribution, timing convergence, and U.S. citizenship.
Perl, Tcl, Innovus, ICC2, PrimeTime, RedHawk, Voltus, Calibre, EDA
2mo
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Senior ASIC/FPGA Verification Engineer (Onsite)
El Segundo or Fullerton
$96k-$182k/yr OnsiteFull Time
5+ YOEActive transferable U.S. SECRET clearance and U.S. citizenship, STEM degree (BS or advanced) with 5+ years (BS) or 3+ years (advanced) experience, RTL verification using VHDL/Verilog/SystemVerilog, testbench and coverage, and revision control (Git/Subversion).
SystemVerilog, OVM, UVM, VHDL, Verilog, Git, Subversion, QuestaSim, Synplify, Quartus, Vivado, Unix, Linux
1mo
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Sr. ASIC Design Verification Engineer, Amazon Leo
Sunnyvale or San Diego or Los Angeles County
$159k-$248k/yr OnsiteFull Time
7+ YOEBachelor's in CS/CE/EE, 7+ years verification experience (communications preferred), 5+ years with UVM and C/C++ and scripting, familiarity with Matlab and formal verification preferred; must meet U.S. export-control eligibility.
UVM, SystemC, DPI-C, Matlab, C/C++, FPGA
2mo
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Senior Principal Engineer, Architecture ASIC / System
Toronto or Ottawa or Burlington or Irvine or Morrisville or Santa Clara or Westborough
$192k-$255k/yr OnsiteFull Time
14+ YOESenior architect with 14+ years in system architecture for SoC; expertise in interconnects, memory hierarchies, power management, security; strong technical leadership.
IP evaluation, IP block, SoC architecture
3mo
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ASIC High Speed AMS Technical Leader
Carlsbad, California, United States
OnsiteFull Time
12+ YOELead analog/mixed-signal design for high-speed optical driver ICs; coordinate full-chip specs, design, verification; mentor engineers; collaborate across teams.
Cadence Virtuoso, Spectre, Caliber, SystemVerilog, Verilog-AMS, Python, C
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Hardware Engineer
Colorado Springs or Irvine or Longmont or Fremont or Rochester or San Jose
$91k-$113k/yr OnsiteFull Time
Early-career candidates pursuing or recently completing an engineering degree; familiarity with hardware, firmware, ASIC/SoC, or systems; programming and design experience through coursework or projects; strong analytical and communication skills.
Verilog/SystemVerilog, RTL, FPGA, C, C++, Assembly, Python, Java, Go, SQL, JavaScript, Git, Linux, IDE, CAD, Microsoft Office, RTOS
2d
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FPGA Verification Engineer, Air Dominance and Strike
Costa Mesa, California, United States
$146k-$194k/yr OnsiteFull Time
2+ YOEBachelor’s degree in electrical or computer engineering, 2+ years of FPGA/ASIC verification experience, SystemVerilog, UVM, SVA, simulators, Git, Linux, and eligibility for a U.S. Secret clearance.
SystemVerilog, UVM, SystemVerilog Assertions (SVA), Questa, VCS, Xcelium, Vivado, Git, Linux, SVUnit, Python, Tcl, Makefile, Ethernet, PCIe, JESD204C, MIL-STD-1553, SPI, CI/CD, Nix, ARM
1mo
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Digital Design Principal Engineer/Manager
Irvine, California, United States
$190k-$225k/yr OnsiteFull Time
20+ YOE20+ years FPGA/SoC development with leadership experience; MS in Electrical Engineering; deep Verilog/SystemVerilog expertise; FPGA/ASIC implementation and packet processing experience; scripting in C/C++, Perl, Tcl, Python.
Verilog, SystemVerilog, AMD (Xilinx Vivado), C, C++, Perl, Tcl, Python, Claude Code, Copilot
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Staff Systems Engineer
Carlsbad, California, United States
$134k-$175k/yr OnsiteFull Time
3+ YOEExperience validating ASICs for optical modules and data center applications, high-speed serial interfaces and re-timer design, signal integrity and DSP expertise, test automation, PCB/simulation (ADS, Cadence, Matlab), BS/MS/PhD with relevant years of experience.
ADS, Cadence, Matlab, PCIe, Ethernet, SerDes
4d
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Principal Physical Design Engineer
San Jose or Irvine
$150k-$250k/yr OnsiteFull Time
5+ YOE5+ years of ASIC physical design experience, advanced-node tapeout expertise, EDA tool proficiency, and expertise in synthesis, power analysis, EM/IR cleanup, timing closure, and physical verification.
System-on-Chips (SoCs), RTL, GDSII, Static Timing Analysis (STA), Design Rule Checking (DRC), Layout Versus Schematic (LVS), Tcl, Python, Perl, Cadence Innovus, Cadence Tempus, Cadence Voltus, Cadence Pegasus, Calibre
1mo
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FPGA Verification Engineer, Air Dominance and Strike (Fastwater Staffing)
Costa Mesa, California, United States
RemoteFull Time
2+ YOEBachelor's in EE/CE, 2+ years FPGA/ASIC verification, proficient in SystemVerilog/UVM/SVA, experience with industry simulators, Git and Linux, eligible for U.S. Secret clearance.
SystemVerilog, UVM, SVA, Questa, VCS, Xcelium, Vivado, Git, Linux, SVUnit, Python, Tcl, Makefile, Nix
1mo
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Principal Electronics Design Engineer
Garden Grove, California, United States
$140k-$190k/yr OnsiteFull Time
10+ YOEBSEE and 10+ years electronic systems design experience, FPGA and embedded microprocessor design, GNSS/M-Code/SAASM, Ethernet/PTP, schematic capture, team leadership, ability to obtain secret clearance and U.S. citizenship.
FPGA, PWB, GNSS, M-Code, SAASM, Ethernet, Precision Time Protocol (PTP), SoC, SoM, ASIC
1mo
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Applications Engineer - FPGA Prototyping
San Diego or Austin or Boulder or Costa Mesa or Pasadena or Tempe or Wilsonville or Fremont
$167k-$334k/yr HybridFull Time
5+ YOE5+ years in design/verification/FPGA/ASIC or similar; BS/MS in EE/CE/CS; active experience with SystemVerilog/Verilog/VHDL, FPGA tools, scripting, simulation and customer-facing technical support.
SystemVerilog, Verilog, VHDL, SystemC, C/C++, Perl, Python, XML, JSON, proFPGA, HAPS, Xilinx Vivado, Altera Quartus, Questa, Incisive, VCS, OVM, UVM
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