85 digital design engineer jobs at 51 companies in Ladera Ranch, CA
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Digital Design Engineer
Irvine, California, United States
$98k-$144k/yr OnsiteFull Time
1+ YOE1+ years experience designing and verifying high-performance communications/DSP ASICs; strong RTL (Verilog/System Verilog) and UNIX-based EDA tool skills; experience with verification, synthesis, lint, CDC, power analysis; MATLAB/C++ a plus.
Verilog, System Verilog, UNIX, EDA, MATLAB, C/C++
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Senior Principal Digital Design Engineer
Irvine, California, United States
$186k-$228k/yr OnsiteFull Time
6+ YOEExpert digital ASIC design experience, SystemVerilog/RTL implementation, block/system verification, synthesis/power/timing analysis, and technical leadership; BS in EE (or advanced) plus extensive experience.
SystemVerilog, Verilog, UVM, SystemC, PCIe, PCI-SIG, IEEE 802.3, SDC
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Digital Design Engineer, Air Dominance and Strike
Costa Mesa, California, United States
$146k-$194k/yr OnsiteFull Time
2+ YOEBachelor's degree in electrical or computer engineering, 2+ years of FPGA, ASIC, or digital design experience, VHDL/Verilog proficiency, Linux, Git, Tcl/Python, and eligibility for a U.S. Secret clearance.
VHDL, Verilog, SystemVerilog, Linux, Git, Tcl, Python, AMD (Xilinx), Intel/Altera, Lattice, AMD (Xilinx) Vitis, Ethernet, PCIe, JESD204, SPI, I2C, UART, CAN, MIL-STD-1553, DO-254, Jira
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Digital Design Principal Engineer/Manager
Irvine, California, United States
$190k-$225k/yr OnsiteFull Time
20+ YOE20+ years FPGA/SoC development with leadership experience; MS in Electrical Engineering; deep Verilog/SystemVerilog expertise; FPGA/ASIC implementation and packet processing experience; scripting in C/C++, Perl, Tcl, Python.
Verilog, SystemVerilog, AMD (Xilinx Vivado), C, C++, Perl, Tcl, Python, Claude Code, Copilot
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ASIC / FPGA Digital Design Engineer – (Associate or Experienced)
El Segundo or Huntington Beach
$99k-$162k/yr OnsiteFull Time
2+ YOEBachelor's degree in a related technical field plus 2+ years of FPGA, ASIC, or SoC digital design experience; HDL development, simulation, debugging, synthesis, digital design fundamentals, and U.S. citizenship required.
ASIC, FPGA, SoC, HDL, RTL
2d
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ASIC / FPGA Digital Design Engineer – (Lead or Senior)
El Segundo or Huntington Beach
$146k-$223k/yr OnsiteFull Time
9+ YOEBachelor's degree in a related technical field and 9+ years of FPGA, ASIC, or SoC digital design experience; HDL, simulation, synthesis, troubleshooting, timing, and CDC knowledge required.
ASIC, FPGA, SoC, HDL, RTL
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Senior Digital Engineer
Sydney or Sydney or Irvine or Boston or Bangalore or Cambridge or Hangzhou or Taipei or Tokyo or Sydney
OnsiteFull Time
5+ YOE5+ years as Senior Digital Engineer; strong Verilog/SystemVerilog; RTL design; low-power techniques; collaborate with firmware/PHY teams.
Verilog/SystemVerilog, C, Python, Tcl, Shell, Makefiles, UPF/CPF, Scripting and automation
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Principal Electrical Design Engineer
Phoenix or Huntsville or Cypress or Andover or Chantilly or Alpharetta or Torrance or Gulf Breeze
OnsiteFull Time
6+ YOEBS in Electrical/Computer Engineering; 6+ years embedded hardware design; high-speed digital design; lead and mentor engineers; travel; security clearance awareness
Cadence Allegro, Mentor, JAMA, DOORS, JIRA, Confluence, FMEA/DFM/DFT
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Electronics Design Engineer
Los Angeles, California, United States
$100k-$130k/yr HybridFull Time
2+ YOEBachelor's degree in electrical or computer engineering, 2+ years of multilayer PCB design, digital communication peripherals, power circuitry, test equipment, and U.S. Person status required.
Altium Designer, Xilinx FPGAs, Vivado IDE, MATLAB, Python, C, DMM, oscilloscope, logic analyzer, spectrum analyzer, Ethernet, USB 2.0, I2C, RS232, FCC, CE Mark, MIL-STD-461
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Electrical Design Engineer
Vista, California, United States
$106k-$125k/yr OnsiteFull Time
8+ YOEBachelor's or master's degree in electrical engineering and 8–10 years of regulated-industry design experience, including embedded programming, analog/digital circuits, hardware, software, and system testing.
FPGA, microprocessors, DSPs, OrCAD, AutoCAD, MPLABX, TI CCS, Microsoft Excel
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Principal Digital Engineer
Los Angeles, California, United States
$125k-$188k/yr OnsiteFull Time
5+ YOEU.S. citizen with active Secret clearance, STEM degree plus relevant experience (Bachelor+5yrs/Master+3yrs/PhD+1yr), experience in high-speed digital design, FPGA/SoC/ASIC and verification, EMV/V&V tools, strong communication.
VHDL, Verilog, System Verilog, System Verilog (UVM), UVM, MATLAB, Simulink
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PCB Design Engineer
Foothill Ranch, California, United States
$115k-$145k/yr OnsiteFull Time
4+ YOE4+ years PCB design experience, proficiency with Altium Designer, multilayer PCB layout, analog/digital circuit knowledge, prototype bring-up, and lab test equipment.
Altium Designer, Draftsman, OutputJob, LTspice, Micro-Cap, Simulink, Gerber, Oscilloscope, Multimeter, Function Generator, Power Supply
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Electrical Engineering Digital Design Lead
Irvine or Los Angeles
OnsiteFull Time
5+ YOETechnical degree or equivalent, minimum 5 years industry experience, advanced 3D design and coordination skills, competency with document management and Microsoft Office, strong understanding of engineering/architectural concepts and standards, excellent communication and organization.
BIM, Microsoft Office
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Electronic Design Engineer, Principal
Morrisville or Long Beach
OnsiteFull Time
10+ YOEBachelor's degree in electrical engineering or equivalent, 10+ years of applicable experience, mixed-signal circuit design, analog and digital controls, power supplies, interfaces, simulation tools, and lab testing experience.
ADS, LTspice, Microwave Office, I2C, CAN, SPI, CPLD, FPGA, RSU
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Digital Design Specialist: Structural Engineering
Irvine or San Diego
$61k-$92k/yr HybridFull Time
4+ YOE4–15 years structural drafting/BIM experience, proficiency in CAD and Revit, strong communication, detail-oriented, able to produce construction documentation; Associate degree in drafting preferred.
CAD, Revit, BIM
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Senior Rail Track Design Engineer
Coral Gables or New York City or Tampa or San Francisco or Houston or Los Angeles or Chicago or Pensacola or Dallas
HybridFull Time
8+ YOESenior track design engineer with 8+ years rail experience, PE licensure, civil engineering degree; BIM/Digital design tools proficiency; lead complex rail projects in the US.
Bentley OpenRail, OpenRoads, InRoads, MicroStation, Civil 3D
2w
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Design Verification Engineer
Broomfield or San Diego or Fort Collins or San Jose or Irvine
$144k-$230k/yr OnsiteFull Time
10+ YOE12+ years verification experience for complex digital and mixed-signal circuits; proficiency with SystemVerilog/UVM/SVA, scripting, simulation tools, and RTL/gate-level debug; BS/MS in EE/CE.
SystemVerilog, UVM, SVA, Synopsys, Cadence, Mentor, Perl, Python, Tcl, DesignSync, git, Palladium, Veloce, Zebu, Xilinx, ICL, PDL, Tessent
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Senior Hardware Engineer, Digital
Long Beach, California, United States
$148k-$222k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE, 5+ years designing electronics for harsh, mission-critical environments; expertise in high-speed interfaces, memory and SoC/microcontroller design; experience with Altium, board bring-up, validation, and cross-functional integration.
eCAD, Altium, SPI, PCIe, Ethernet
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Principal Engineer Digital FPGA/Sr. Principal Engineer Digital FPGA (Level 3/4)
Manhattan Beach, California, United States
$125k-$235k/yr OnsiteFull Time
5+ YOERequires Top Secret clearance, STEM degree, 5+ years engineering experience (level-dependent), FPGA and electronic design/test experience, strong communication skills.
FPGA, PCB, CCA, Electronic Test System
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Senior Avionics FPGA Design & Verification Engineer - TeraWave
Seattle or Los Angeles or Denver
$157k-$220k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
7+ YOE7+ years in digital design/SoC architecture; SystemVerilog/Verilog RTL; FPGA/SoC integration; timing and bus protocols; RTL simulation and debugging; hardware design verification.
SystemVerilog, Verilog, QuestaSim, FPGA, SoC, RTL, AXI, AHB
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