169 asic engineer jobs at 32 companies in Lockhart, TX
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ASIC Engineer, Architecture
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
6+ YOE6+ years in ASIC/silicon engineering with experience in performance modeling; proficiency in C++ and Python; BS in CS/CE or equivalent; experience with SystemC, assembly, and ASIC performance analysis.
C++, Python, SystemC, CUDA, SystemVerilog, VHDL
1mo
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ASIC Engineer, Annapurna Labs
Austin, Texas, United States
OnsiteFull Time
Bachelor's in Electrical Engineering (required); design and verification experience for ASICs/SoCs; strong SystemVerilog skills; experience debugging architectures and verifying IP-to-system levels; familiarity with microarchitecture, synthesis, timing, and RTL development.
SystemVerilog, Python, Perl, ARM
1mo
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Senior ASIC Verification Engineer
Austin, Texas, United States
$136k-$265k/yr HybridFull Time
5+ YOEBS/MS in Electrical or Computer Engineering (or equivalent), 5+ years design verification experience, UVM/SystemVerilog, ASIC flow, Perl or Python, familiarity with synthesis/simulation and debug tools.
SystemVerilog, UVM, Perl, Python, dc_shell, VCS, Debussy, GDB
2mo
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ASIC Physical Design Engineer
Maynard or Austin
$136k-$195k/yr HybridFull Time
5+ YOEBachelors in Engineering with 5+ years or Masters in Engineering with 3+ years in ASIC physical design; experience with floorplanning, place-and-route, STA, timing closure, DFT collaboration, scripting, and design flow optimization.
Cadence Innovus, Synopsys ICC2, Synopsys DC/FC, Synopsys Formality, Cadence LEC, Tempus, Python, TCL, Perl
2mo
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Sr. ASIC DFT Engineer (Silicon)
Irvine or Austin or Sunnyvale
$125k-$150k/yr OnsiteFull Time
5+ YOEBachelor's in engineering or physics; 5+ years in DFT/semiconductor testing; strong ASIC/DFT/ATE expertise.
Siemens Tessent, ATPG, Teradyne, Advantest, Perl, Python, Tcl, C++, IEEE 1500, IEEE 1687, IST
1w
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Principal ASIC Design Engineer - Terawave
San Diego or Kent or Austin or California
$269k-$377k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
10+ YOEBS/MS in Electrical Engineering or related,10+ years experience in complex SoC/ASIC design and verification,Verilog/System Verilog,ARM integration,DSP and high-speed interfaces,post-silicon bring-up experience.
Verilog, System Verilog, Matlab, SystemC, C, FPGA, AXI, PCIE, ARM
6d
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ASIC Digital Design Engineer Lead
Austin, Texas, United States
OnsiteFull Time
Senior engineering leader with strong ASIC/digital design background, supplier engagement, cross-functional communication, and schedule-driven delivery.
4d
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Senior ASIC Design Engineer – Clocks IP
Santa Clara or Austin
$136k-$265k/yr HybridFull Time
3+ YOEBS in Electrical Engineering or equivalent, 3+ years relevant ASIC/RTL experience, Verilog and Python skills, strong knowledge of logic optimization and PPA trade-offs, excellent collaboration and communication.
Verilog, python
1w
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ASIC Verification Engineer
Austin, Texas, United States
HybridFull Time
10+ YOE10+ years debugging RTL, SystemVerilog/UVM proficiency, RTL testbench architecture, knowledge of SerDes/PCIe/ARM/DSP/Ethernet domains, scripting (TCL/Python/Perl), BS/MS in EE/CS.
SystemVerilog, UVM, TLM, TCL, Python, Perl
2mo
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ASIC Verification Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOE5+ years verification experience, 2+ full block/system verification cycles, deep VLSI verification knowledge, experience with SystemVerilog/UVM/eRM, familiarity with data-paths/protocols (Ethernet preferred), mentoring and cross-team collaboration.
SystemVerilog, UVM, eRM, RTL, Ethernet
1mo
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Senior Staff ASIC CAD Flow Infrastructure Engineer
Austin, Texas, United States
$129k-$191k/yr OnsiteFull Time
5+ YOE5+ years ASIC CAD/EDA or infrastructure engineering experience, proficiency in Python, Tcl, Shell, Linux, experience supporting Synopsys/Cadence/Siemens EDA tools, strong ASIC/SoC design-flow knowledge, bachelor’s degree in CS/EE (advanced degree or equivalent experience acceptable).
Python, Tcl, Shell, Linux, Synopsys, Cadence, Siemens EDA, EDA
1mo
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ASIC Design Verification Engineer
Austin, Texas, United States
$156k-$268k/yr OnsiteFull Time
Develop and execute IP verification architectures and test plans using System Verilog, UVM, SystemC, Verilog and C/C++; debug regressions, analyze coverage, and participate in code reviews. BS/MS in engineering or CS required. This role is not eligible for visa sponsorship.
System Verilog, UVM, SystemC, Verilog, C, C++, Linux, Windows, VIP
3mo
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Senior ASIC Design Engineer
Austin or United States
RemoteFull Time
8+ YOE8+ years in digital design with Verilog/SystemVerilog; RTL design for high-speed data paths; Ethernet host adapters; timing closure; system-level debug; strong communication.
Verilog, SystemVerilog, EDA tools, timing analysis
2mo
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Software Engineer, ASIC
Austin or South San Francisco
$123k-$216k/yr OnsiteFull Time
Bachelor's degree in computer science or related field; experience with EDA compute environments; proficiency in Rust/Go/C++; Linux storage and datacenter systems; multi-cloud/hybrid deployments; embedded cross-compilation toolchains.
Rust, Python, Go, Cadence, Terraform, Ansible, Packer, MAAS, Bazel, Nix, Prometheus, ClickHouse, Grafana, Ray, Docker, Kubernetes, AWS, OCI, RHEL, Ubuntu
1mo
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ASIC Design Verification Engineer (Santa Clara, CA)
Santa Clara or Austin
$127k-$190k/yr OnsiteFull Time
3+ YOE3+ years DV experience using UVM/assertion-based verification; experience verifying SoC/subsystems, caches, DDR, memory VIPs, DDR PHY, formal verification, PASIM, C++ and Python exposure; bachelor's/master's/PhD in science or engineering.
UVM, SystemVerilog, C++, Python, PASIM, UPF
1w
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ASIC Verification Engineer (788514)
Austin, Texas, United States
HybridFull Time
10+ YOE10+ years RTL verification experience, strong SystemVerilog/UVM and testbench architecture skills, experience in SerDes/PCIe/ARM/DSP/Ethernet domains, scripting (TCL, Python, Perl), BS/MS in EE or CS.
SystemVerilog, UVM, TLM, TCL, Python, Perl
1mo
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Senior Staff Application Engineer
Austin, Texas, United States
OnsiteFull Time
10+ YOEMS in Engineering required, 10+ years in power management, experience with firmware-enabled products and large-scale ASIC/SoC power, multiphase DC/DC converters, mixed-signal ICs, control loop theory, FPGA prototyping, lab equipment and automation.
FPGA, ASIC, Network Analyzer, Oscilloscope, Waveform Generator
2d
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Product Power Engineer
Santa Clara or Hsinchu or Austin or Bengaluru
$179k-$219k/yr OnsiteFull Time
3+ YOEMS/PhD in CS or Computer Architecture,3+ years power benchmarking/analysis experience,knowledge of architecture/logic/circuit power impacts,ASIC power analysis experience,and strong problem-solving skills.
RISC-V, RTL, FPGA, ASIC
2mo
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Staff Systems Engineer (Austin, TX, US)
Austin, Texas, United States
$114k-$220k/yr OnsiteFull Time
6+ YOEMSEE 6+ years or BSEE 8+ years with systems design; MATLAB; SystemVerilog, UVM, RNM; FPGA/ASIC design; lab equipment; RF/PLL knowledge.
MATLAB, SystemVerilog, UVM, RNM, FPGA, ASIC
3d
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EDA Tools SW Engineer
Hillsboro or Santa Clara or Austin or Phoenix
$174k-$330k/yr HybridFull Time
6+ YOEBS+10/ MS+8/ PhD+6 in Electrical/Computer Engineering or related,6+ years relevant experience, technical leadership, foundry/process/ASIC physical design and verification knowledge.
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