39 asic engineer jobs at 23 companies in New York
1w
Save
Mark Applied
Hide
ASIC Engineer
New York City, New York, United States
$250k-$300k/yr OnsiteFull Time
4+ YOE4+ years RTL design and verification experience; ASIC design using Synopsys or Cadence flows; experience in front-end, back-end or verification; FPGA/ASIC familiarity; programming experience (Python, C++, Java, Haskell); willingness to learn OCaml.
Hardcaml, OCaml, Synopsys, Cadence, Python, C++, Java, Haskell
5d
Save
Mark Applied
Hide
ML ASIC Design Engineer
Mountain View or New York City
$175k-$215k/yr HybridFull Time
5+ YOEBS in Computer Engineering or equivalent experience; 5+ years with SystemVerilog, ASIC RTL design, and microarchitecture; 3+ years designing high-performance CPU, GPU, or NPU cores; Python or C++.
SystemVerilog, Python, C++, Chisel, Scala
14h
Save
Mark Applied
Hide
ASIC & FPGA Design Engineer
Liverpool, New York, United States
$98k-$182k/yr OnsiteFull Time
7+ YOEBachelor's degree in a relevant engineering or computer science field, 7+ years of relevant experience, FPGA architecture and design expertise, technical leadership, VHDL, DSP knowledge, and ability to obtain a Secret clearance.
ASIC, FPGA, AMD Xilinx, Altera, VHDL, Xilinx Vivado, Intel Quartus, Microsemi Libero, Mentor Questa HDL simulator, UVM, MATLAB, Nvidia CUDA, OpenCL, Simulink HDL Coder, Xilinx System Generator, Microprocessors, DSPs, Interface Controllers
1mo
Save
Mark Applied
Hide
ASIC/FPGA Design Engineer IV
Littleton or California or Massachusetts or New York or Colorado or Hawaii or Illinois or Maryland or Minnesota or New Jersey or Vermont or Washington or District of Columbia
$124k-$218k/yr OnsiteFull Time
5+ YOEUS citizen able to obtain and maintain DoD Secret clearance, BS in Computer/Electrical Engineering or equivalent, 5+ years professional experience, HDL experience (VHDL/Verilog/SystemVerilog), ASIC/FPGA design and verification experience, Linux proficiency.
VHDL, Verilog, SystemVerilog, Linux, Microsoft Project, Microsoft Office, Atlassian JIRA, Earned Value Management System (EVMS)
3w
Save
Mark Applied
Hide
Senior Digital ASIC Design Engineer
Upton, New York, United States
$115k-$145k/yr OnsiteFull Time
7+ YOEBachelor's in EE/CE/applied physics, 7+ years digital ASIC design, SystemVerilog/Verilog RTL, CAD/EDA tool experience, strong timing/CDC/low-power knowledge, and collaboration with mixed-signal, verification, and firmware teams.
SystemVerilog, Verilog, Cadence, Synopsys, Siemens, AXI, AHB, APB, Wishbone, I2C, SPI, JTAG, Tcl, Python, Perl, Make, shell
2mo
Save
Mark Applied
Hide
Staff Engineer, Digital ASIC Design (CONTRACT)
Burlington or New York
HybridContract
8+ YOEBS/MS/PhD in EE/CE; 8+ yrs in digital IC/ASIC/SoC; RTL ownership; SystemVerilog/Verilog; high-throughput datapaths; silicon constraints; SV/UVM; Python/cocotb; post-silicon bring-up.
SystemVerilog/Verilog, UVM, Python, cocotb, RTL, RTL verification, Fixed-point modeling
1mo
Save
Mark Applied
Hide
ASIC Technical Lead- DFT
San Jose or New York City or New York or Washington or Illinois or United States or Canada
$211k-$305k/yr HybridFull Time
10+ YOEBachelor's or Master's in Electrical/Computer Engineering with 10+ years experience; expertise in JTAG, scan and BIST architectures, ATPG and EDA toolsets (TestMax, Tetramax, Tessent, PrimeTime); SystemVerilog/Verilog and post-silicon debug experience.
JTAG, ATPG, TestMax, Tetramax, Tessent, PrimeTime, System Verilog, Verilog
1mo
Save
Mark Applied
Hide
Hardware Engineer (FPGA/ASIC)
New York, New York, United States
$300k/yr OnsiteInternship
Comfortable with a programming language; experience with hardware description languages (VHDL, Verilog, Chisel, Pymtl) and FPGA/ASIC projects; familiar with vendor tools (Vivado, Quartus, Genus, Innovus).
Hardcaml, OCaml, VHDL, Verilog, Chisel, Pymtl, Vivado, Quartus, Genus, Innovus
1w
Save
Mark Applied
Hide
Hardware Engineer III
Gurgaon or New York City
HybridFull Time
3+ YOEBachelor's degree in electrical engineering or equivalent experience; 3–5 years in ASIC/FPGA development and verification; expertise in Verilog, SystemVerilog/VHDL, Xilinx tools, networking, Linux, Python, and C/C++.
Verilog, SystemVerilog, VHDL, Xilinx, cocotb, UVM, Linux, Shell scripting, Python, C, C++, FPGA, ASIC, Ethernet, PCIe
4w
Save
Mark Applied
Hide
Two Sigma Securities, Hardware Engineer
New York City, New York, United States
$165k-$300k/yr HybridFull Time
1+ YOEMinimum 1 year RTL design and verification experience, proficiency in SystemVerilog and Python, FPGA/ASIC knowledge, timing analysis, network protocol familiarity; C++ is a plus.
SystemVerilog, Python, FPGA, ASIC, C++
3w
Save
Mark Applied
Hide
Principal Engineer - Design
Hauppauge, New York, United States
$75k-$232k/yr OnsiteFull Time
10+ YOEBachelor's in Electrical Engineering or equivalent,10+ years relevant experience,Verilog/System Verilog proficiency,experience with Ethernet/USB/PCIe and ASIC design/verification,strong problem solving and communication skills.
Verilog, System Verilog, Xilinx FPGA
2mo
Save
Mark Applied
Hide
FPGA Engineer
Amsterdam or Chicago or London or New York City or Singapore
OnsiteFull Time
Professional FPGA/ASIC design and verification experience; SystemVerilog/Verilog/VHDL and C++; familiarity with EDA tools and scripting (TCL, Python, Bash); university degree in EE/CS/CE or related.
SystemVerilog, Verilog, VHDL, C++, TCL, Python, Bash, EDA
1mo
Save
Mark Applied
Hide
FPGA Engineer
New York or New Jersey or United States
RemoteFull Time
5+ YOE5–7 years FPGA/ASIC experience, DSP proficiency, RTL (VHDL/Verilog/SystemVerilog), FPGA toolchains, high-speed interfaces, MATLAB/Simulink or Python, and SoC/embedded integration experience.
VHDL, Verilog, SystemVerilog, Xilinx Vivado, Vitis, Intel Quartus, JESD204, LVDS, SERDES, MATLAB, Simulink, Python, RFSoC, Xilinx/AMD Versal, Zynq, Git, eCPRI, Ethernet
1mo
Save
Mark Applied
Hide
RTL Design Engineer
New York City or Palo Alto or London
$205k-$285k/yr HybridFull Time
Production SystemVerilog RTL experience, verification with UVM/cocotb/formal, taped-out silicon, ASIC/SoC design background, simulation and timing collaboration experience.
SystemVerilog, UVM, cocotb, formal, Chipyard, OpenTitan, CVA6, RISC-V
2mo
Save
Mark Applied
Hide
Digital Modem Engineer
Austin or Chicago or New York City or London
$150k-$250k/yr OnsiteFull Time
5+ YOE5+ years in digital modem design, modeling, and implementation; strong FPGA/ASIC knowledge; Python/C/C++/Matlab; MS/PhD in EE/CS or equivalent.
Python, C++, C, Matlab
1mo
Save
Mark Applied
Hide
Embedded Software Engineer - Platform & Hardware Integration
Endicott or United States
$100k-$140k/yr HybridFull Time
4+ YOEU.S. citizen with bachelor’s in engineering, 4+ years embedded avionics/controls experience, expertise in low‑level C/C++/assembly, SoC bring‑up, FPGA/ASIC integration, TSN/PCIe/AFDX, ARM DS IDE/DSTREAM and Python.
C, C++, Assembly, ARM DS IDE, DSTREAM, Python, TSN, PCIe, AFDX
4d
Save
Mark Applied
Hide
Hardware Machine Learning Engineer
Chicago or New York City
$200k-$225k/yr OnsiteFull Time
Experience with hardware constraints, FPGA or ASIC mapping, ML inference optimization, Python or C++, and hardware development tools; strong cross-disciplinary communication skills.
VHDL, SystemVerilog, hls4ml, FINN, Vitis AI, PyTorch, TensorFlow, Python, C++, MLIR, TVM, XLA, UVM, Cocotb
1mo
Save
Mark Applied
Hide
Research Engineer, Chip Design RL (Reinforcement Learning)
San Francisco or New York City
$500k-$850k/yr HybridFull Time
Bachelor's or equivalent, expertise in ASIC/FPGA design and EDA tools, experience with RTL, verification (UVM, formal methods), physical design and tapeout experience; RL experience and tooling experience preferred.
EDA tools, UVM, formal methods, place-and-route
2w
Save
Mark Applied
Hide
Principal Technical Engineer 3rd Party IP Engineer
Morrisville or Austin or New York or Burlington or Westborough or Boise
$152k-$225k/yr OnsiteFull Time
3+ YOEBachelor’s in CS/EE with 5-10 years or Master/PhD with 3-5 years; deep DDR/LPDDR/GDDR/HBM/eMMC interface knowledge, ASIC design flow experience, 3rd-party IP management, project and customer communication skills.
DDR, LPDDR, GDDR, HBM, eMMC, logic synthesis, physical design, timing, DRC/LVS, Formal verification, Design-For-Test, DFT
1mo
Save
Mark Applied
Hide
Integrated Circuit Design Verification Engineer
Vancouver or Washington or California or New York City
$147k-$259k/yr OnsiteFull Time
10+ YOE10+ years of ASIC design verification experience, BSEE or MSEE (or equivalent), strong UVM/SystemVerilog skills, Siemens Questa experience, scripting (TCL/Make/Perl/Python/Shell), and excellent communication.
UVM, SystemVerilog, Siemens Questa, TCL, Make, Perl, Python, Shell, Linux
Explore Jobs
Expand Your Job Search
Top Cities in New York for Asic Engineer
- Asic Engineer jobs in New York, NY
- Asic Engineer jobs in Brooklyn, NY
- Asic Engineer jobs in Queens, NY
- Asic Engineer jobs in Manhattan, NY
- Asic Engineer jobs in The Bronx, NY
- Asic Engineer jobs in Staten Island, NY
- Asic Engineer jobs in Buffalo, NY
- Asic Engineer jobs in Rochester, NY
- Asic Engineer jobs in Yonkers, NY
- Asic Engineer jobs in Syracuse, NY
- Asic Engineer jobs in Amherst, NY
- Asic Engineer jobs in Albany, NY
- Asic Engineer jobs in Greenburgh, NY
- Asic Engineer jobs in New Rochelle, NY
- Asic Engineer jobs in Cheektowaga, NY
- Asic Engineer jobs in Mount Vernon, NY
- Asic Engineer jobs in Schenectady, NY
- Asic Engineer jobs in Utica, NY
- Asic Engineer jobs in White Plains, NY
- Asic Engineer jobs in Clay, NY