Pleasant Hill • 50 milesRemote · Hybrid · Onsite · Field · All Environments
Pleasant Hill • 50 milesRemote · Hybrid · Onsite · Field · All Environments
Pleasant Hill • 50 milesRemote · Hybrid · Onsite · Field · All Environments
Pleasant Hill • 50 milesRemote · Hybrid · Onsite · Field · All Environments
539 asic engineer jobs at 89 companies in Pleasant Hill, CA
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ASIC Engineer, Architecture
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
6+ YOE6+ years in ASIC/silicon engineering with experience in performance modeling; proficiency in C++ and Python; BS in CS/CE or equivalent; experience with SystemC, assembly, and ASIC performance analysis.
C++, Python, SystemC, CUDA, SystemVerilog, VHDL
1mo
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ASIC Design Engineer
Santa Clara, California, United States
$127k-$190k/yr OnsiteFull Time
5+ YOE5+ years ASIC/SoC design and micro-architecture experience; expertise in RTL design, clocking, CDC/lint analysis, AMBA protocols; proficiency in Python and Perl; experience across full ASIC lifecycle.
Python, Perl, ARM CoreSight, AMBA, AHB, APB, AXI, PCIe, USB, FPGA, SoC
1w
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ASIC Verification Engineer
Sunnyvale, California, United States
$120k-$243k/yr HybridFull Time
3+ YOERequires 3+ years of ASIC/SoC verification experience, strong SystemVerilog and UVM expertise, and experience with test planning, coverage, assertions, simulation, and waveform debugging.
SystemVerilog, UVM, Cadence Xcelium, Synopsys VCS, Mentor Questa, Jenkins, UPF
1w
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ASIC Verification Engineer
Sunnyvale, California, United States
$120k-$243k/yr HybridFull Time
3+ YOERequires 3+ years of ASIC/SoC verification experience, strong SystemVerilog and UVM expertise, and proficiency with test planning, coverage, assertions, randomization, and simulation debugging.
SystemVerilog, UVM, Cadence Xcelium, Synopsys VCS, Mentor Questa, Jenkins, UPF
1w
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ASIC Verification Engineer
Sunnyvale, California, United States
$120k-$243k/yr HybridFull Time
3+ YOERequires 3+ years of ASIC/SoC verification experience, SystemVerilog and UVM expertise, test planning, coverage analysis, assertions, randomization, and simulation-tool proficiency.
SystemVerilog, UVM, Cadence Xcelium, Synopsys VCS, Mentor Questa, Jenkins, UPF
4w
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ASIC Implementation Engineer STA
San Jose, California, United States
$144k-$230k/yr OnsiteFull Time
12+ YOEBachelor's in EE or Computer Engineering, 12+ years ASIC STA experience, proficiency with Cadence or Synopsys sign-off flows, SDC/constraint development, and scripting in Tcl, Python, or Perl.
Tcl, Python, Perl, Shell, Cadence, Synopsys
1d
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Senior ASIC Design Engineer
San Jose, California, United States
$168k-$245k/yr OnsiteFull Time
7+ YOEBachelor’s degree in Electrical or Computer Engineering plus 7+ years, master’s plus 4+ years, or PhD plus 1+ year of ASIC design experience; Verilog/SystemVerilog experience required.
Verilog, SystemVerilog, scripting
1w
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Mid Level ASIC Design Engineer
Sunnyvale or Munich
OnsiteFull Time
3+ YOERequires 3+ years of ASIC RTL design experience with Verilog or SystemVerilog, CPU IP integration, processor architecture and interface knowledge, front-end ASIC tools, low-power design, and a bachelor's degree in electrical or computer engineering.
Verilog, SystemVerilog, ARM, RISC-V, MIPS, AMBA, APB, AXI, SPI, eMMC, MII, GPIO, I2C, UPF
1mo
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Senior ASIC Design Engineer
Santa Clara or United States
$136k-$265k/yr HybridFull Time
5+ YOE5+ years ASIC or SoC design experience; BS/MS in relevant engineering or equivalent; RTL design, logic synthesis, timing analysis, SOC integration experience; strong scripting/programming (Perl, Python, C++).
Perl, Python, C++
16h
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ASIC & FPGA Design Engineer Stf - E4
Littleton or Sunnyvale or Denver or Boulder or Louisville or Highlands Ranch or King of Prussia
$136k-$252k/yr OnsiteFull Time
Bachelor of Science in Electrical Engineering or related field, or equivalent experience; ASIC/FPGA design, debugging, or verification experience; active Top Secret clearance and U.S. citizenship required.
ASIC, FPGA, Microsoft Project, Microsoft Office, Atlassian JIRA, Earned Value Management System (EVMS)
1mo
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Senior ASIC Design Engineer
Santa Clara or California
$136k-$265k/yr HybridFull Time
5+ YOEBS/MS or equivalent,5+ years ASIC/SoC design experience,RTL design,logic synthesis,timing analysis,and strong scripting in Perl/Python/C++.
Perl, Python, C++, ARM
2mo
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Sr. ASIC DFT Engineer (Silicon)
Irvine or Austin or Sunnyvale
$125k-$150k/yr OnsiteFull Time
5+ YOEBachelor's in engineering or physics; 5+ years in DFT/semiconductor testing; strong ASIC/DFT/ATE expertise.
Siemens Tessent, ATPG, Teradyne, Advantest, Perl, Python, Tcl, C++, IEEE 1500, IEEE 1687, IST
5d
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ML ASIC Design Engineer
Mountain View or New York City
$175k-$215k/yr HybridFull Time
5+ YOEBS in Computer Engineering or equivalent experience; 5+ years with SystemVerilog, ASIC RTL design, and microarchitecture; 3+ years designing high-performance CPU, GPU, or NPU cores; Python or C++.
SystemVerilog, Python, C++, Chisel, Scala
3mo
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ASIC Design Engineer - Pixel IP DMA
Sunnyvale or San Francisco
OnsiteFull Time
10+ YOEBachelor's degree with 10 years experience in front-end ASIC RTL design; strong collaboration and communication skills; experience with DMA engines, memory controllers, interconnects, and AMBA protocols.
RTL, Synthesis, AMBA (AXI, AHB, APB)
2w
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ASIC Design Engineer
San Jose, California, United States
OnsiteFull Time
BS/MS/PhD in Electrical/Computer Engineering; proficiency in RTL design using Verilog/SystemVerilog, logic and micro-architecture, familiarity with AMBA/PCIe/NAND/DDR, scripting (Python/Perl/TCL), and Linux command-line.
Verilog, SystemVerilog, AMBA, PCIe, NAND, DDR, Python, Perl, TCL, Linux
2mo
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ASIC Formal Verification Engineer, TPU Compute
Sunnyvale, California, United States
$163k-$237k/yr OnsiteFull Time
8+ YOEBachelor's in Electrical/Computer Engineering or Computer Science; 8 years in silicon/ASIC/SoC design; experience with SystemVerilog Assertions and formal verification.
2mo
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ASIC/FPGA Verification Engineer III
Denver or Highlands Ranch or King of Prussia or Sunnyvale
$101k-$178k/yr OnsiteFull Time
3+ YOEB.S. in Electrical Engineering or equivalent, 3+ years professional ASIC/FPGA verification experience, SystemVerilog and UVM/OVM/VMM proficiency, HDL and scripting experience, ability to obtain/maintain DoD Secret clearance (US citizenship required).
SystemVerilog, Universal Verification Methodology (UVM), OVM, VMM, VHDL, Verilog, Linux, Perl, TCL, Python
2mo
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Principal Engineer, ASIC Design Verification
San Jose, California, United States
$190k-$240k/yr OnsiteFull Time
12+ YOEMS in Electrical or Computer Engineering; 12+ years ASIC/SoC verification experience; SystemVerilog and UVM expert; verification environment design; scripting for automation.
SystemVerilog, UVM, Scripting (Python, Perl, Tcl, Shell)
3mo
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ASIC Verification Engineer
San Jose, California, United States
OnsiteFull Time
8+ YOE8+ years in UVM verification; RTL/gate-level verification; test plan and testbench development in C/Assembly/SystemVerilog; AMBA AXI/AHB/APB; PCIe/USB/Ethernet; scripting; repository and bug-tracking tools.
UVM, SystemVerilog, C, Assembly, Python, Shell, Perl, AMBA AXI, AHB, APB, PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART, Git, JIRA, Bitbucket, Jenkins
2mo
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Principal Analog/Mixed-Signal ASIC Engineer
Sunnyvale, California, United States
$258k-$294k/yr HybridFull Time
10+ YOEPh.D. in EE or related field, 10+ years ASIC AMS and/or high-speed design experience, leading ASIC tape-outs, top-level ASIC architecture ownership, DRC/LVS/PI/SI verification experience, strong communication.
Register-Transfer Level (RTL), SOS, Git, Calibre
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