42 asic engineer jobs at 22 companies in River Edge, NJ
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ASIC Engineer
New York City, New York, United States
$250k-$300k/yr OnsiteFull Time
4+ YOE4+ years RTL design and verification experience; ASIC design using Synopsys or Cadence flows; experience in front-end, back-end or verification; FPGA/ASIC familiarity; programming experience (Python, C++, Java, Haskell); willingness to learn OCaml.
Hardcaml, OCaml, Synopsys, Cadence, Python, C++, Java, Haskell
1w
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ML ASIC Design Engineer
Mountain View or New York City
$175k-$215k/yr HybridFull Time
5+ YOEBS in Computer Engineering or equivalent experience; 5+ years with SystemVerilog, ASIC RTL design, and microarchitecture; 3+ years designing high-performance CPU, GPU, or NPU cores; Python or C++.
SystemVerilog, Python, C++, Chisel, Scala
2mo
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Staff Engineer, Digital ASIC Design (CONTRACT)
Burlington or New York
HybridContract
8+ YOEBS/MS/PhD in EE/CE; 8+ yrs in digital IC/ASIC/SoC; RTL ownership; SystemVerilog/Verilog; high-throughput datapaths; silicon constraints; SV/UVM; Python/cocotb; post-silicon bring-up.
SystemVerilog/Verilog, UVM, Python, cocotb, RTL, RTL verification, Fixed-point modeling
2mo
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ASIC Technical Lead- DFT
San Jose or New York City or New York or Washington or Illinois or United States or Canada
$211k-$305k/yr HybridFull Time
10+ YOEBachelor's or Master's in Electrical/Computer Engineering with 10+ years experience; expertise in JTAG, scan and BIST architectures, ATPG and EDA toolsets (TestMax, Tetramax, Tessent, PrimeTime); SystemVerilog/Verilog and post-silicon debug experience.
JTAG, ATPG, TestMax, Tetramax, Tessent, PrimeTime, System Verilog, Verilog
1mo
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Hardware Engineer (FPGA/ASIC)
New York, New York, United States
$300k/yr OnsiteInternship
Comfortable with a programming language; experience with hardware description languages (VHDL, Verilog, Chisel, Pymtl) and FPGA/ASIC projects; familiar with vendor tools (Vivado, Quartus, Genus, Innovus).
Hardcaml, OCaml, VHDL, Verilog, Chisel, Pymtl, Vivado, Quartus, Genus, Innovus
3w
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Senior Engineer, Physical Design Engineering (ASIC)
Somerset County or Wilmington
$117k-$161k/yr OnsiteFull Time
5+ YOEExpertise in ASIC/SoC physical design, floorplanning, P&R, timing closure, physical verification, scripting (TCL/Python), and cross-functional collaboration; 5+ years experience preferred.
Cadence, TCL, Python
2w
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Hardware Engineer III
Gurgaon or New York City
HybridFull Time
3+ YOEBachelor's degree in electrical engineering or equivalent experience; 3–5 years in ASIC/FPGA development and verification; expertise in Verilog, SystemVerilog/VHDL, Xilinx tools, networking, Linux, Python, and C/C++.
Verilog, SystemVerilog, VHDL, Xilinx, cocotb, UVM, Linux, Shell scripting, Python, C, C++, FPGA, ASIC, Ethernet, PCIe
2mo
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AI Research Engineer, Pre-Training
London or New York City
$250k-$300k/yr OnsiteFull Time
2+ YOERequires 2+ years building deep learning systems and strong engineering skills in areas such as CUDA, Triton, Pallas, CuTe DSL, PyTorch, JAX, XLA, CUDA Graphs, FPGA, or ASICs.
CUDA, Triton, Pallas, CuTe DSL, PyTorch, JAX, XLA, CUDA Graphs, FPGA, ASIC
1w
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PMTS Silicon Design Engineer
Fishkill, New York, United States
$175k-$250k/yr OnsiteFull Time
5+ YOEMaster’s in computer, electrical, or electronic engineering plus 5 years of experience, or bachelor’s plus 7 years. Requires Verilog RTL, processor architecture, ASIC implementation, verification, timing, power management, DFT/DFD, and Perl, Shell, or Tcl scripting.
Verilog, Perl, Shell, Tcl, CPU, SOC, ASIC, Design-for-Test (DFT), Design-for-Debug (DFD)
1mo
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Two Sigma Securities, Hardware Engineer
New York City, New York, United States
$165k-$300k/yr HybridFull Time
1+ YOEMinimum 1 year RTL design and verification experience, proficiency in SystemVerilog and Python, FPGA/ASIC knowledge, timing analysis, network protocol familiarity; C++ is a plus.
SystemVerilog, Python, FPGA, ASIC, C++
1w
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Senior Principal FPGA Design Engineer
Manchester or Totowa
OnsiteFull Time
8+ YOERequires 8+ years relevant experience with a bachelor's degree, FPGA or ASIC design, VHDL or Verilog HDL, timing analysis, high-speed interfaces, simulation, scripting, and Secret clearance eligibility.
FPGA, ASIC, VHDL, Verilog HDL, Xilinx Vivado, Intel Quartus, Altera Quartus, Modelsim, Questa, GIT, CVS, Clearcase, Subversion, Perl, Tcl, Python, SERDES, PCIe, DDR2, DDR3, DDR4, LVDS, ADC, DAC
4w
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Principal Engineer - Design
Hauppauge, New York, United States
$75k-$232k/yr OnsiteFull Time
10+ YOEBachelor's in Electrical Engineering or equivalent,10+ years relevant experience,Verilog/System Verilog proficiency,experience with Ethernet/USB/PCIe and ASIC design/verification,strong problem solving and communication skills.
Verilog, System Verilog, Xilinx FPGA
2mo
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FPGA Engineer
Amsterdam or Chicago or London or New York City or Singapore
OnsiteFull Time
Professional FPGA/ASIC design and verification experience; SystemVerilog/Verilog/VHDL and C++; familiarity with EDA tools and scripting (TCL, Python, Bash); university degree in EE/CS/CE or related.
SystemVerilog, Verilog, VHDL, C++, TCL, Python, Bash, EDA
1mo
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RTL Design Engineer
New York City or Palo Alto or London
$205k-$285k/yr HybridFull Time
Production SystemVerilog RTL experience, verification with UVM/cocotb/formal, taped-out silicon, ASIC/SoC design background, simulation and timing collaboration experience.
SystemVerilog, UVM, cocotb, formal, Chipyard, OpenTitan, CVA6, RISC-V
2mo
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Digital Modem Engineer
Austin or Chicago or New York City or London
$150k-$250k/yr OnsiteFull Time
5+ YOE5+ years in digital modem design, modeling, and implementation; strong FPGA/ASIC knowledge; Python/C/C++/Matlab; MS/PhD in EE/CS or equivalent.
Python, C++, C, Matlab
1d
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Responsible Systems Engineer V, Avionics, Secret clearance
Littleton or Englewood or Littleton or Colorado or Sunnyvale or California or New York City or New Jersey or Denver or Pennsylvania or Connecticut or Dallas or Florida or Grand Prairie or Marietta or Camden or Kentucky or Ocala or Lufkin or Washington
$145k-$270k/yr OnsiteFull Time
8+ YOEBachelor's degree in electrical engineering or related field, 8+ years' experience, avionics systems design and integration expertise, technical leadership, Agile and Model Based Engineering experience, and active DoD Secret clearance.
Model Based Engineering, Agile, Flight Computers, FPGA, ASIC, AI
1w
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Hardware Machine Learning Engineer
Chicago or New York City
$200k-$225k/yr OnsiteFull Time
Experience with hardware constraints, FPGA or ASIC mapping, ML inference optimization, Python or C++, and hardware development tools; strong cross-disciplinary communication skills.
VHDL, SystemVerilog, hls4ml, FINN, Vitis AI, PyTorch, TensorFlow, Python, C++, MLIR, TVM, XLA, UVM, Cocotb
1mo
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Research Engineer, Chip Design RL (Reinforcement Learning)
San Francisco or New York City
$500k-$850k/yr HybridFull Time
Bachelor's or equivalent, expertise in ASIC/FPGA design and EDA tools, experience with RTL, verification (UVM, formal methods), physical design and tapeout experience; RL experience and tooling experience preferred.
EDA tools, UVM, formal methods, place-and-route
1mo
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Integrated Circuit Design Verification Engineer
Vancouver or Washington or California or New York City
$147k-$259k/yr OnsiteFull Time
10+ YOE10+ years of ASIC design verification experience, BSEE or MSEE (or equivalent), strong UVM/SystemVerilog skills, Siemens Questa experience, scripting (TCL/Make/Perl/Python/Shell), and excellent communication.
UVM, SystemVerilog, Siemens Questa, TCL, Make, Perl, Python, Shell, Linux
1mo
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Senior Network Solution Engineer (Weekend Coverage)
Santa Clara or Westford or Austin or Durham or Redmond or New York
$140k-$270k/yr OnsiteFull Time
5+ YOE5+ years software development (C, C++, Python, or Go) in the networking industry, 5+ years supporting in-field production network equipment, bachelor's degree or equivalent, experience with Linux NIC drivers/ASICs/firmware/network OS, expert Ethernet/IP knowledge.
C, C++, Python, Go, Linux, InfiniBand, NVLink, Spectrum-X
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