364 asic engineer jobs at 57 companies in Rodeo, CA
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ASIC Engineer, Architecture
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
6+ YOE6+ years in ASIC/silicon engineering with experience in performance modeling; proficiency in C++ and Python; BS in CS/CE or equivalent; experience with SystemC, assembly, and ASIC performance analysis.
C++, Python, SystemC, CUDA, SystemVerilog, VHDL
1mo
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ASIC Design Engineer
Santa Clara, California, United States
$127k-$190k/yr OnsiteFull Time
5+ YOE5+ years ASIC/SoC design and micro-architecture experience; expertise in RTL design, clocking, CDC/lint analysis, AMBA protocols; proficiency in Python and Perl; experience across full ASIC lifecycle.
Python, Perl, ARM CoreSight, AMBA, AHB, APB, AXI, PCIe, USB, FPGA, SoC
3mo
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ASIC Design Engineer lll
Sunnyvale, California, United States
$120k-$243k/yr OnsiteFull Time
4+ YOEBachelor’s in electrical engineering with 4+ years ASIC design experience; Verilog/SystemVerilog; SVA; EDA tools; strong problem solving.
Verilog, SystemVerilog, SVA, EDA Tools, Perl, Python
6d
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ASIC Verification Engineer
Sunnyvale, California, United States
$120k-$243k/yr HybridFull Time
3+ YOERequires 3+ years of ASIC/SoC verification experience, SystemVerilog and UVM expertise, test planning, coverage analysis, assertions, randomization, and simulation-tool proficiency.
SystemVerilog, UVM, Cadence Xcelium, Synopsys VCS, Mentor Questa, Jenkins, UPF
6d
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ASIC Verification Engineer
Sunnyvale, California, United States
$120k-$243k/yr HybridFull Time
3+ YOERequires 3+ years of ASIC/SoC verification experience, strong SystemVerilog and UVM expertise, and experience with test planning, coverage, assertions, simulation, and waveform debugging.
SystemVerilog, UVM, Cadence Xcelium, Synopsys VCS, Mentor Questa, Jenkins, UPF
5d
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Mid Level ASIC Design Engineer
Sunnyvale or Munich
OnsiteFull Time
3+ YOERequires 3+ years of ASIC RTL design experience with Verilog or SystemVerilog, CPU IP integration, processor architecture and interface knowledge, front-end ASIC tools, low-power design, and a bachelor's degree in electrical or computer engineering.
Verilog, SystemVerilog, ARM, RISC-V, MIPS, AMBA, APB, AXI, SPI, eMMC, MII, GPIO, I2C, UPF
4w
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Senior ASIC Design Engineer
Santa Clara or United States
$136k-$265k/yr HybridFull Time
5+ YOE5+ years ASIC or SoC design experience; BS/MS in relevant engineering or equivalent; RTL design, logic synthesis, timing analysis, SOC integration experience; strong scripting/programming (Perl, Python, C++).
Perl, Python, C++
4w
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Senior ASIC Design Engineer
Santa Clara or California
$136k-$265k/yr HybridFull Time
5+ YOEBS/MS or equivalent,5+ years ASIC/SoC design experience,RTL design,logic synthesis,timing analysis,and strong scripting in Perl/Python/C++.
Perl, Python, C++, ARM
2mo
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Sr. ASIC DFT Engineer (Silicon)
Irvine or Austin or Sunnyvale
$125k-$150k/yr OnsiteFull Time
5+ YOEBachelor's in engineering or physics; 5+ years in DFT/semiconductor testing; strong ASIC/DFT/ATE expertise.
Siemens Tessent, ATPG, Teradyne, Advantest, Perl, Python, Tcl, C++, IEEE 1500, IEEE 1687, IST
2d
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ML ASIC Design Engineer
Mountain View or New York City
$175k-$215k/yr HybridFull Time
5+ YOEBS in Computer Engineering or equivalent experience; 5+ years with SystemVerilog, ASIC RTL design, and microarchitecture; 3+ years designing high-performance CPU, GPU, or NPU cores; Python or C++.
SystemVerilog, Python, C++, Chisel, Scala
3mo
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ASIC Design Engineer - Pixel IP DMA
Sunnyvale or San Francisco
OnsiteFull Time
10+ YOEBachelor's degree with 10 years experience in front-end ASIC RTL design; strong collaboration and communication skills; experience with DMA engines, memory controllers, interconnects, and AMBA protocols.
RTL, Synthesis, AMBA (AXI, AHB, APB)
2mo
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ASIC Formal Verification Engineer, TPU Compute
Sunnyvale, California, United States
$163k-$237k/yr OnsiteFull Time
8+ YOEBachelor's in Electrical/Computer Engineering or Computer Science; 8 years in silicon/ASIC/SoC design; experience with SystemVerilog Assertions and formal verification.
2mo
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ASIC/FPGA Verification Engineer III
Denver or Highlands Ranch or King of Prussia or Sunnyvale
$101k-$178k/yr OnsiteFull Time
3+ YOEB.S. in Electrical Engineering or equivalent, 3+ years professional ASIC/FPGA verification experience, SystemVerilog and UVM/OVM/VMM proficiency, HDL and scripting experience, ability to obtain/maintain DoD Secret clearance (US citizenship required).
SystemVerilog, Universal Verification Methodology (UVM), OVM, VMM, VHDL, Verilog, Linux, Perl, TCL, Python
2mo
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Principal Analog/Mixed-Signal ASIC Engineer
Sunnyvale, California, United States
$258k-$294k/yr HybridFull Time
10+ YOEPh.D. in EE or related field, 10+ years ASIC AMS and/or high-speed design experience, leading ASIC tape-outs, top-level ASIC architecture ownership, DRC/LVS/PI/SI verification experience, strong communication.
Register-Transfer Level (RTL), SOS, Git, Calibre
2mo
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ASIC Design Engineer (eInfochips)
Mountain View, California, United States
OnsiteFull Time
5+ YOE5+ years Verilog/SystemVerilog design; Fusion Compiler experience; scripting; PCIe and AXI interfaces; ARM Fabric IP; IPXACT; EDA tools.
Fusion Compiler, VCS, Questa CDC, Spyglass Lint, Design Compiler, Genus, UPF, Python, Tcl, Perl, Verilog, SystemVerilog, AXI, AMBA, IPXACT
6d
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ASIC III - AMZ10291241
Sunnyvale, California, United States
$237k-$248k/yr OnsiteFull Time
5+ YOEMaster's and 5 years' experience, or bachelor's and 7 years' progressive experience, in computer science, engineering, or related field. Requires 5 years with STA, Tcl/Perl/Python automation, physical design flows, and SoC design.
Tcl, Perl, Python, Static Timing Analysis (STA), LSF, RTL, SoC
2mo
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SR ASIC Design Engineer - Ethernet Switch & High-Speed I/O
Santa Clara, California, United States
$175k-$300k/yr OnsiteFull Time
BS or MS in Electrical/Computer Engineering; experience with ASIC/RTL design; knowledge of Ethernet, SerDes, and high-speed I/O; scripting (Perl/Python/Shell); experience with SystemVerilog/Verilog; VCS; strong communication and problem-solving skills.
VCS, SystemVerilog, Verilog, Perl, Python, Shell, RTL design, SerDes
1mo
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ASIC DFT STA Engineer
San Jose or Santa Clara
$165k-$241k/yr OnsiteFull Time
1+ YOEDegree plus relevant years of experience (BSc+7 / MSc+4 / PhD+1). Experience with RTL, CDC/RDC, conformal verification, SDC development, timing constraint development, and scripting (Perl, Tcl, Python, Makefile).
Perl, Tcl, Python, Makefile, Synopsys TCM, Synopsys PrimeTime, Synopsys Fusion, Synopsys Design Compiler, Tessent, Conformal
2mo
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Software Engineer, ASIC
Austin or South San Francisco
$123k-$216k/yr OnsiteFull Time
Bachelor's degree in computer science or related field; experience with EDA compute environments; proficiency in Rust/Go/C++; Linux storage and datacenter systems; multi-cloud/hybrid deployments; embedded cross-compilation toolchains.
Rust, Python, Go, Cadence, Terraform, Ansible, Packer, MAAS, Bazel, Nix, Prometheus, ClickHouse, Grafana, Ray, Docker, Kubernetes, AWS, OCI, RHEL, Ubuntu
2mo
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ASIC Architect
Sunnyvale, California, United States
OnsiteFull Time
10+ YOEMasters or PhD in Electrical/Computer Engineering; 10+ years performance analysis and modeling experience across GPUs/CPUs/accelerators; strong computer architecture background; ability to build performance models in Python.
Python
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