23 asic engineer jobs at 10 companies in Sanborn, NY
2mo
Save
Mark Applied
Hide
Principal Analog ASIC Design Engineer
Toronto, Ontario, Canada
OnsiteFull Time
10+ YOE10+ years in analog/mixed-signal ASIC/IC design; leadership; tapeouts; high-voltage and low-noise analog blocks.
Cadence, EDA, Simulation And Verification
3mo
Save
Mark Applied
Hide
Senior ASIC Verification Engineer, Coherent High Speed Interconnect
Toronto, /, Canada
$125k-$175k/yr HybridFull Time
3+ YOESenior ASIC verification engineer with 3+ years of experience in high-speed interconnect verification, TBs, SV/UVM, and C/C++.
SystemVerilog, UVM, VCS, Debussy, GDB, C++
2mo
Save
Mark Applied
Hide
Senior ASIC Verification Engineer, Coherent High Speed Interconnect
Toronto, Ontario, Canada
$125k-$205k/yr HybridFull Time
3+ YOE3+ years verification experience; bachelor's (or master's) degree or equivalent; experience with SV/UVM, C++, testbench architecture, functional coverage, assertions, and tools like VCS, Debussy, GDB; knowledge of PCIe, CXL, CHI.
C++, System Verilog, SV, UVM, VCS, Debussy, GDB, PCIe, CXL, CHI
1mo
Save
Mark Applied
Hide
ASIC Digital Design, Architect
Markham or Mississauga or Nepean or Ottawa
HybridFull Time
10+ YOE10+ years ASIC digital design experience with high-speed/mixed-signal systems, mastery of Verilog or VHDL, CDC, synthesis and DFT knowledge, mentorship experience, and ability to define digital/analog interfaces.
Verilog, VHDL
2mo
Save
Mark Applied
Hide
Senior Principal Engineer, Architecture ASIC / System
Toronto or Ottawa or Burlington or Irvine or Morrisville or Santa Clara or Westborough
$192k-$255k/yr OnsiteFull Time
14+ YOESenior architect with 14+ years in system architecture for SoC; expertise in interconnects, memory hierarchies, power management, security; strong technical leadership.
IP evaluation, IP block, SoC architecture
5d
Save
Mark Applied
Hide
Connectivity Project Engineer, Principal
Toronto, Ontario, Canada
OnsiteFull Time
6+ YOE5+ MgmtRequires a science or engineering degree and 6–8+ years of ASIC experience, with 15 years in semiconductor development, 5+ years in technical leadership, SoC expertise, and project trade-off experience.
SerDes, DDR, Ethernet, PCIe
3w
Save
Mark Applied
Hide
Sr. Design for Test (DFT) Engineer
Toronto or Mountain View or Boston
HybridFull Time
13+ YOEBachelor's in Electrical Engineering, 13+ years DFT experience on ASICs, 2+ tapeouts, experience with DFT CAD/ATPG, Python/TCL scripting, post-silicon bring-up and ATE interfacing.
Python, TCL, SystemVerilog, ATPG, ATE
1mo
Save
Mark Applied
Hide
FPGA Development Tools Engineer
Toronto, Ontario, Canada
$100k-$130k/yr OnsiteFull Time
3+ YOEBachelor's in CS/EE/CE or related, 3+ years' experience, proficiency in C/C++, familiarity with compiler concepts, FPGA/ASIC flows, and teamwork/communication skills.
C/C++, MLIR, LLVM, Clang, Git, Verilog, VHDL, Xilinx Vivado HLS, Intel HLS, HLS
2mo
Save
Mark Applied
Hide
Software and Hardware Senior Engineering Specialist (SWEL)
Dorval or Montreal or Toronto or United States
OnsiteFull Time
15+ YOEBachelor's in engineering, 15+ years engineering experience (10+ in aerospace), 5+ years FPGA/ASIC/embedded software experience, expertise with aerospace certification standards, DOORS/JAMA, C/C++/Ada95/Assembly/Python, and OIQ membership.
RTCA DO-178B/C, DO-248B/C, DO-254, DO-330, EASA CM-SWCEH-001, EASA CM-SWCEH-002, FAA AC 20-115D, FAA AC 20-152A, FAA Order 8110.49A, FAA Order 8110.105A, DOORS, JAMA, C, C++, Ada95, Assembly, Python
2d
Save
Mark Applied
Hide
Sr. Manager, Physical Design Engineering, Annapurna Labs
Toronto, Ontario, Canada
$180k-$300k/yr OnsiteFull Time
10+ YOE5+ MgmtRequires 10+ years ASIC/SoC physical design, 5+ years managing teams of 8+ engineers, multiple advanced-node tapeouts, RTL-to-GDSII expertise, EDA proficiency, and expert TCL, Python, and Perl scripting.
Synopsys, Fusion Compiler, ICC2, PrimeTime, StarRC, RedHawk-SC, Cadence, Innovus, Tempus, Quantus, Voltus, Siemens Calibre, TCL, Python, Perl, RTL2GDS, AI/ML, PDK, UPF, UCIe, CoWoS, EMIB, InFO, SoIC, Foveros, CXL, TSMC, Samsung, Intel Foundry Services, IEEE
3mo
Save
Mark Applied
Hide
Debug Architect
Toronto, Ontario, Canada
HybridFull Time
Experienced in hardware debug for CPU, SoC, or ASIC systems; strong processor architecture knowledge (RISC-V/x86/ARM); familiar with debug, profiling, and trace methodologies (iJTAG); comfortable across hardware/software boundaries; proficient in HDL (Verilog/VHDL) and Python/Git.
Verilog, VHDL, Python, Git
Explore Jobs