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475 design verification engineer jobs at 99 companies in Berkeley, CA

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Design Verification Engineer
San Francisco, California, United States
OnsiteFull Time
Apple
AppleNASDAQ: AAPL: Designs and sells consumer electronics, software, and online services.
Digital-focused design verification for pre-silicon IP: DV methodology, test-plan and verification environment development, test writing, debug, coverage, and RTL sign-off for tape-out.
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1mo
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Design Verification Engineer
San Jose, California, United States
$144k-$230k/yr OnsiteFull Time
Broadcom
BroadcomNASDAQ: AVGO: Designs and sells semiconductors and infrastructure software to enterprises.
12+ YOEBachelor's in EE/electronic engineering or CS required; 12+ years experience; strong System Verilog, UVM/OVM, RTL, C/C++, Perl, SystemC skills; ASIC design verification, debugging, and coverage experience; US work authorization required.
System Verilog, UVM, OVM, RTL, C/C++, Perl, SystemC, Emulators, FPGA
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Principal Design Verification Engineer
Austin or Texas or Santa Clara or Malta
$153k-$290k/yr OnsiteFull Time
GlobalFoundries
GlobalFoundriesNASDAQ: GFS: Semiconductor foundry providing chip design and fabrication services.
8+ YOEBachelor's in engineering, 8+ years design verification (CPU/SoC) experience, hands-on SystemVerilog/UVM and constrained-random verification, scripting in Python/Perl/Shell, familiarity with CPU architectures and cache/coherency concepts.
SystemVerilog, UVM, C, Assembly, Python, Perl, Shell
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Principal Design Verification Engineer
Austin or Santa Clara
$153k-$290k/yr OnsiteFull Time
GlobalFoundries
GlobalFoundriesNASDAQ: GFS: Manufacturer of semiconductors and provider of wafer fabrication services.
8+ YOE8+ years in design verification of CPU/SoC, SystemVerilog/UVM, constrained random verification, and scripting.
SystemVerilog, UVM, Python, Perl, Shell
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Design Verification Engineer - SoC
San Jose, California, United States
$150k-$275k/yr OnsiteFull Time
Etched
Etched: Designs specialized AI chips optimized for transformer architectures.
Design verification for ASIC/SoC; SystemVerilog and Python; performance modeling; test benches and verification infrastructure.
SystemVerilog, Python
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Design Verification Engineer
Sunnyvale, California, United States
$190k-$230k/yr OnsiteFull Time
Cerebras Systems
Cerebras SystemsNasdaq: CBRS: Manufactures specialized computer chips designed for AI.
3+ YOE3+ years design verification experience; deep knowledge of SystemVerilog, DPI, UVM; strong programming (object-oriented) skills; experience with testbenches, simulation, emulation, and silicon bring-up.
SystemVerilog, DPI, UVM, Python, Perl
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Design Verification Engineer
Santa Clara, California, United States
$146k-$250k/yr OnsiteFull Time
AMD
AMDNASDAQ: AMD: Designs and manufactures computer processors and graphics technology.
SystemVerilog/UVM verification expertise; IP/subsystem/SoC verification; testbench development; strong debugging and collaboration.
SystemVerilog, UVM, VCS, Verdi/DVE, Python, Shell, Tcl, Make
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Design Verification Engineer
Mountain View, California, United States
$120k-$475k/yr HybridFull Time
MatX
MatX: Developing custom silicon chips optimized for large language models.
Concept-to-silicon verification experience with SystemVerilog, UVM, ABV, and scripting; production verification and silicon bring-up experience preferred.
SystemVerilog, Python, C/C++, Bluespec, UVM, assertion-based verification (ABV)
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Design Verification Engineer
Raleigh or Hillsboro or Austin or Mountain View or Redmond
$102k-$202k/yr HybridFull Time, Contract
Microsoft
MicrosoftNASDAQ: MSFT: Develops software, services, devices, and cloud computing solutions.
1+ YOEMaster's+1 or Bachelor's+2 years technical engineering experience (or equivalent); verification of silicon/IP using UVM/System Verilog/Formal; Python scripting; knowledge of CHI/AMBA/PCIe/CXL preferred; pass Microsoft Cloud Background Check and export-control screening.
UVM, Formal, System Verilog, Python
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Staff Engineer, Design Verification
Santa Clara, California, United States
$114k-$171k/yr OnsiteFull Time
Marvell
MarvellNASDAQ: MRVL: Designs and develops high-performance semiconductor and infrastructure solutions.
3+ YOEBachelor's in Computer/Electrical Engineering + 3+ years (2+ with MS/PhD); System Verilog/UVM, verification test-plan development, verification tools, C/C++, Python/Perl, and Linux proficiency.
System Verilog/UVM, C/C++, Python, Perl, Linux, CXL, PCIE, Ethernet, ARM
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Design Verification Engineer
Santa Clara, California, United States
$142k-$200k/yr HybridFull Time
Intel
IntelNasdaq: INTC: Designs and manufactures microprocessors and semiconductor components.
3+ YOEBS/MS in EE/CS (3+ years DV), hands-on coding in SystemVerilog, C, C++, Python, experience with UVM/ABV and simulation/formal verification, familiarity with interconnect protocols and AI-assisted development tools.
SystemVerilog, C, C++, Python, UVM, ABV, JasperGold, VC Formal, AI-assisted development tools, emulation, FPGA
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2mo
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Design Verification Engineer - APS
Santa Clara, California, United States
OnsiteFull Time
Texas Instruments
Texas InstrumentsNASDAQ: TXN: Designs and manufactures semiconductors and integrated circuits.
8+ YOEBachelor's degree in electrical engineering; 8+ years of experience; UVM, Verilog, SystemVerilog, Python experience; mixed-signal verification; scalable testbenches; team mentoring.
UVM, Verilog, SystemVerilog, Python, EDA tools
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Design Verification Engineer IV
San Jose, California, United States
$112k-$176k/yr OnsiteFull Time
Arrow Electronics
Arrow ElectronicsNYSE: ARW: Distributes electronic components and enterprise computing solutions globally.
6+ YOEExpertise in SystemVerilog/UVM, AXI/PCIe/Ethernet/NOC/UCIe protocols, CPU architectures (ARM, RISC-V) and C/C++; 6–8+ years verification experience; formal verification and scripting experience; ability to architect SoC verification environments.
SystemVerilog (SV), UVM, AXI, NOC, Ethernet, PCIe, UCIe, ARM, RISC-V, C, C++
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Senior Design Verification Engineer
Tempe or Independence or Arizona or Ohio or San Jose or New York City
$142k-$224k/yr HybridFull Time
Viasat
ViasatNASDAQ: VSAT: Provider of global satellite-based connectivity and secure communication solutions.
8+ YOE8+ years design verification experience with UVM and testbench development; Bachelor's in EE/CE or related; experience with Questa/Xcelium/VCS; AI/agentic DV experience preferred; US citizenship and ability to obtain Secret clearance; travel up to 10%.
UVM, SystemVerilog, VHDL, Verilog, Questa, Xcelium, VCS, Jira
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ASIC Engineer, Design Verification
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
Meta
MetaNASDAQ: META: Develops social networking platforms and virtual reality technologies.
6+ YOEBachelor's in CS/CE or equivalent; 6+ years SystemVerilog/UVM or C/C++ verification and IP/SoC level verification experience; EDA tools and scripting (Python, TCL, Perl, Shell).
SystemVerilog, UVM, C, C++, Python, TCL, Perl, Shell, Mercurial, Hg, Git, SVN, SV Assertions, Formal, Emulation, PCIe, RoCE, DDR, HBM, Ethernet
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2mo
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Design Verification (DV) Engineer
Mountain View or Austin
$200k-$320k/yr OnsiteFull Time
DensityAI
DensityAI: Designing custom AI hardware accelerators for large language models.
Expert SystemVerilog and UVM verification skills; hands-on experience with logic simulators and waveform debuggers; coverage-driven verification, assertion and regression infrastructure experience; optional formal, Python/Tcl scripting, and RISC-V familiarity.
SystemVerilog, UVM, Synopsys VCS, Cadence Xcelium, Synopsys Verdi, Cadence SimVision, Python, Tcl, LLVM, RISC-V
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3mo
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GPU Design Verification Engineer
San Diego or Santa Clara or Boxborough or Austin
$162k-$273k/yr OnsiteFull Time
Qualcomm
QualcommNASDAQ: QCOM: Designs and manufactures semiconductors and wireless telecommunications products.
2+ YOEBachelor's +4 yrs (or Master's +3 / PhD +2) in Comp Eng/CS/EE; experience in hardware/software/systems engineering; verification skills with System Verilog/UVM, Verilog/VHDL, C/C++; scripting and emulation exposure preferred.
System Verilog, UVM, Verilog, VHDL, C/C++, Python, Make, Airflow, Veloce, Palladium, Zebu, FPGA, Protium, HAPS, qemu, GNU Toolchain, Visual Studio, gdb, uboot, uefi, Vulkan, DX11, DX12, Windows, Linux
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Senior Design Verification Engineer
San Jose, California, United States
$168k-$336k/yr OnsiteFull Time
Micron Technology
Micron TechnologyNASDAQ: MU: Designs and manufactures semiconductor memory and data storage solutions.
5+ YOE5+ years UVM/System Verilog design verification experience, BS in EE/CS required (MS preferred), GenAI and agentic MCP experience, ASIC simulation and SoC/CPU emulation expertise, System Verilog/System C/C++ skills, test plan and coverage closure experience.
GenAI, agentic MCP, UVM, System Verilog, System C, C++
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CPU Design Verification Engineer
Mountain View, California, United States
$138k-$198k/yr OnsiteFull Time
Google
GoogleNASDAQ: GOOGL: Provides online search, advertising, cloud computing, and consumer electronics.
3+ YOEBachelor's in EE/CE/CS (or equivalent), 3+ years verification experience with UVM/SystemVerilog, B.S. required; preferred MS/PhD, low-power verification, scripting (Python/Perl/Shell/Bash), ARM ISA, and Linux/Android knowledge.
Universal Verification Methodology (UVM), SystemVerilog, Python, Perl, Shell, Bash, Advanced RISC Machine (ARM), Linux, Android
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2mo
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SMTS Design Verification Engineer
Minneapolis or Boise or Folsom or Richardson or San Jose
$178k-$389k/yr OnsiteFull Time
Micron Technology
Micron TechnologyNASDAQ: MU: Manufacturer of semiconductor memory and data storage products.
6+ YOEBS/MS/PhD in EE/CE or related; 6+ years UVM/SystemVerilog functional verification; experience building UVM testbenches, coverage-driven methodology, protocol/interface verification, RTL/testbench debug, and post-silicon bring-up support.
UVM, SystemVerilog, SystemVerilog Assertions (SVA), JasperGold, VC Formal, Verilog-AMS, Real-number modeling (RNM), ATE
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