Camp Pendleton North • 50 milesRemote · Hybrid · Onsite · Field · All Environments
Camp Pendleton North • 50 milesRemote · Hybrid · Onsite · Field · All Environments
Camp Pendleton North • 50 milesRemote · Hybrid · Onsite · Field · All Environments
Camp Pendleton North • 50 milesRemote · Hybrid · Onsite · Field · All Environments
126 design verification engineer jobs at 44 companies in Camp Pendleton North, CA
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ASICS Design Verification Engineer
San Diego, California, United States
$116k-$173k/yr OnsiteFull Time
2+ YOEBachelor's in engineering or science and 2+ years ASIC design/verification experience (Master's/PhD alternatives available). Experience with SystemVerilog/UVM, testbench development, coverage, assertions, UPF, formal verification, and scripting (Perl/Python).
SystemVerilog-UVM, SystemVerilog, Verilog, VHDL, C, C++, Perl, Python, UVM, OVM, Unified Power Format (UPF), AMBA, AXI, AHB, APB
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PHY Design Verification Engineer
San Diego, California, United States
OnsiteFull Time
Work on PHY design verification, emulation, test and validation for wireless SoC development.
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Design Verification Engineer
Aliso Viejo or San Jose or Córdoba or Toronto
OnsiteFull Time
3+ YOEBachelors in EE/CE/CS,3+ years verification experience, SystemVerilog/UVM, coverage-driven verification, C/C++ and scripting (Python,Tcl,Perl),test planning and debug skills.
SystemVerilog, UVM, C, C++, Python, Tcl, Perl
3w
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Design Verification Engineer
Broomfield or San Diego or Fort Collins or San Jose or Irvine
$144k-$230k/yr OnsiteFull Time
10+ YOE12+ years verification experience for complex digital and mixed-signal circuits; proficiency with SystemVerilog/UVM/SVA, scripting, simulation tools, and RTL/gate-level debug; BS/MS in EE/CE.
SystemVerilog, UVM, SVA, Synopsys, Cadence, Mentor, Perl, Python, Tcl, DesignSync, git, Palladium, Veloce, Zebu, Xilinx, ICL, PDL, Tessent
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Design Verification Engineer
San Diego, California, United States
$81k-$142k/yr OnsiteFull Time
3+ YOEBachelor's in engineering (or equivalent experience); 3+ years engineering experience; strong knowledge of ASME Y14.100 and Y14.5, PDM experience, ability to read/interprete drawings, lead teams, and obtain DoD clearance.
Product Data Management (PDM)
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Design Verification Engineer - Viasat Government
Marlborough or Carlsbad
$133k-$210k/yr OnsiteFull Time
5+ YOEBachelor's in Electrical or Computer Engineering; 5+ years hardware verification with SystemVerilog/UVM; RTL verification; strong SystemVerilog/UVM; experience with industry EDA tools; US citizenship and active Secret clearance; willingness to travel up to 10%
SystemVerilog, UVM, Siemens Questa, Cadence, Synopsys, Mentor, Python, TCL
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Senior Design Verification Engineer
Mountain View or Hillsboro or Redmond or San Diego
$120k-$235k/yr HybridFull Time
Experience creating emulation/simulation environments, verification using System Verilog/UVM, scripting (Python/Ruby/Perl), Verilog/C/C++, FPGA/emulation experience, and ability to meet export/security screening.
Zebu, Palladium, Verilog, System Verilog, UVM, C, C++, Python, Ruby, Perl, FPGAs, Makefiles
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GPU Design Verification Engineer
San Diego, California, United States
$180k-$301k/yr OnsiteFull Time
10+ YOEMS/PhD or equivalent,10+ years ASIC design verification experience,SystemVerilog/UVM,constrained random,functional coverage,hw/sw co-simulation,emulation,strong debugging and GPU architecture knowledge.
SystemVerilog, UVM, emulation
3mo
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Principal Design Verification Engineer (Silicon Engineering)
Sunnyvale or Austin or Irvine or Redmond
$210k-$310k/yr OnsiteFull Time
10+ YOEBachelor’s in electrical/computer engineering or computer science; 10+ years in design verification and test bench development.
UVM, OVM, VMM, Python, RTL
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Staff Design Verification Test Engineer
Costa Mesa, California, United States
$191k-$253k/yr OnsiteFull Time
12+ YOEBachelor's degree in engineering, physics, or related field; 12+ years in test, verification, or product engineering; RF/microwave measurement, DVT, NPI, failure triage, and engineering leadership experience.
Lattice OS, spectrum analyzers, signal analyzers, VNAs, signal generators, power meters
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Design Verification Engineer - Viasat Government
Marlborough or Carlsbad
$133k-$210k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE or related,5+ years hardware verification experience with SystemVerilog/UVM,experience with industry EDA tools,US citizenship and active Secret clearance required,ability to travel up to 10%.
SystemVerilog, UVM, Siemens Questa, Cadence, Synopsys, Mentor, AMD/Xilinx Vivado, Altera Quartus, Microchip Libero, TCL, Perl, Python, Linux
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Satellite Design Verification Engineer, Amazon Leo
Austin or Sunnyvale or Redmond or San Diego
$136k-$184k/yr OnsiteFull Time
5+ YOE2+ years UVM, C, SystemC, and scripting; 5+ years verification for communication systems; Bachelor's degree in Electrical Engineering.
UVM, C, SystemC, DPI-C, SystemVerilog, Matlab
2mo
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Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)
San Diego or Nashua or Austin or Totowa or California or New Hampshire or Texas or New Jersey or United States
$130k-$222k/yr OnsiteFull Time
8+ YOEBachelor's degree with 8+ years (or equivalent experience); eligible for Secret clearance; experience with SystemVerilog/UVM/OVM and/or VHDL, Mentor Questa or Cadence tools; FPGA/ASIC verification, test plan development, and strong communication.
SystemVerilog, UVM, OVM, VHDL, Mentor Questa, Cadence, Perl, Python, C++, Java, Git, Jira, BitBucket, Matlab, Simulink
5d
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ASIC / FPGA Design Verification Engineer - (Associate or Experienced)
El Segundo or Huntington Beach
$99k-$162k/yr OnsiteFull Time
2+ YOEBachelor's degree and 2+ years of ASIC, FPGA, or SoC verification experience, or master's with related coursework. Requires digital verification fundamentals, SystemVerilog, U.S. citizenship, and ability to obtain Secret clearance.
SystemVerilog, UVM, UVC
5d
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ASIC / FPGA Design Verification Engineer - (Associate or Experienced)
El Segundo or Huntington Beach
$99k-$162k/yr OnsiteFull Time
2+ YOEBachelor's degree or equivalent in a related technical field, 2+ years of relevant verification experience or related master's coursework, digital verification fundamentals, SystemVerilog, U.S. citizenship, and ability to obtain a Secret clearance.
SystemVerilog, UVM
2w
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TPU Design Verification Engineering Lead
Mountain View or San Diego
$192k-$278k/yr OnsiteFull Time
10+ YOE10+ MgmtBachelor's degree or equivalent practical experience; 10 years managing functional verification for IPs and SoCs. Expertise in verification methods including formal, GLS, UPF, UVM, and C-based testing.
GLS, UPF, UVM, C
4w
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Principal Modem PHY IP Design Verification Engineer - Terawave
Texas or California or San Diego
$269k-$377k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
10+ YOEBachelor's in EE/CE/CS,10+ years verification experience, SystemVerilog and UVM expertise, modem PHY/DSP familiarity, scripting with Python/Perl/shell, strong RTL/testbench debugging, ability to work with cross-functional teams.
SystemVerilog, UVM, Python, Perl, shell, MATLAB, C/C++
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Sr. Principal Digital Design Verification Lead
San Diego, California, United States
$142k-$213k/yr HybridFull Time
6+ YOEExperience in FPGA verification using SystemVerilog/UVM, Questa/ModelSim, scripting (Python/Tcl/Bash), Git, RTL (Verilog/VHDL); ability to obtain US Secret clearance and Program Access (PAR).
SystemVerilog, UVM, Questa, ModelSim, Verilog, VHDL, SVA, Python, Tcl, Bash, Git
1w
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RFIC design engineer
Irvine, California, United States
OnsiteFull Time
Requires advanced understanding of RFIC design, simulation, layout, and verification; deep submicron process experience; industrial experience; and a Ph.D. or Master of Science in Electrical Engineering.
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Sr. Principal Digital Design Verification Lead
San Diego, California, United States
$142k-$213k/yr HybridFull Time
5+ YOE5+ years FPGA verification experience, strong SystemVerilog/UVM skills, Questa/ModelSim experience, RTL knowledge (Verilog/VHDL), scripting (Python/Tcl/Bash), Git, and ability to obtain US Secret clearance and Program Access.
SystemVerilog, UVM, Questa, ModelSim, Verilog, VHDL, SVA, Python, Tcl, Bash, Git
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