79 design verification engineer jobs at 41 companies in Dedham, MA
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Staff Engineer, Design Verification Engineering
Wilmington, Massachusetts, United States
$172k-$210k/yr HybridFull Time
4+ YOEMaster's+4yrs or Bachelor's+6yrs in relevant engineering; experience with System Verilog and UVM, metric-driven verification, simulation debug, IP/VIP integration, verification planning, and scripting for automation.
UVM, System Verilog
2mo
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Design Verification Engineer - Viasat Government
Marlborough or Carlsbad
$133k-$210k/yr OnsiteFull Time
5+ YOEBachelor's in Electrical or Computer Engineering; 5+ years hardware verification with SystemVerilog/UVM; RTL verification; strong SystemVerilog/UVM; experience with industry EDA tools; US citizenship and active Secret clearance; willingness to travel up to 10%
SystemVerilog, UVM, Siemens Questa, Cadence, Synopsys, Mentor, Python, TCL
1mo
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ASIC Design Verification Engineer
Irvine or Andover or Broomfield
$129k-$207k/yr OnsiteFull Time
3+ YOEConstrained-random design verification experience using System Verilog/UVM, coverage-driven methodologies, experience with VCS/Incisive and scripting (Python/Perl). Degree with significant related experience required (varies by degree).
System Verilog, UVM, VCS, Incisive, Python, Perl
2w
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Senior Staff Engineer, Design Verification
Westborough, Massachusetts, United States
$151k-$223k/yr OnsiteFull Time
3+ YOEBachelor's with 5+ years or Master's/PhD with 3+ years in digital design/verification; expertise in UVM, constrained-random verification, SVA, RTL debug; C/C++ and scripting (Python/Perl); Linux experience.
UVM, SystemVerilog, SystemVerilog Assertions (SVA), C, C++, Python, Perl, Linux
2mo
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Design Verification Engineer - Viasat Government
Marlborough or Carlsbad
$133k-$210k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE or related,5+ years hardware verification experience with SystemVerilog/UVM,experience with industry EDA tools,US citizenship and active Secret clearance required,ability to travel up to 10%.
SystemVerilog, UVM, Siemens Questa, Cadence, Synopsys, Mentor, AMD/Xilinx Vivado, Altera Quartus, Microchip Libero, TCL, Perl, Python, Linux
1mo
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Senior Staff Design Verification Engineer – Coherent Interconnect
Boston or Austin
OnsiteFull Time
8+ YOE8+ years ASIC/SoC design verification experience, strong SystemVerilog and Python skills, deep knowledge of cache-coherent interconnects and protocols (CHI, ACE, CXL, AXI), BS/MS in EE/CE/CS, strong communication and leadership.
SystemVerilog, Python
2mo
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CPU Design Verification Engineer
Boston or Cambridge
OnsiteFull Time
10+ YOE BS+ with 10+ years experience; CPU architecture, digital logic, testplan/testbenches; C/C++ or SystemVerilog.
C, C++, SystemVerilog
3w
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Design Verification Engineer – Physical AI Compute
Santa Clara or Austin or Boston
$75k-$275k/yr OnsiteFull Time
Experience verifying complex digital/SoC systems with SystemVerilog/UVM, C/C++, assertions, formal, emulation and debugging across HW/SW boundaries.
SystemVerilog, UVM, C, C++, formal verification, emulation, FPGA
2mo
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Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)
Nashua or Manchester or Largo or New Hampshire or Florida or United States
$130k-$222k/yr OnsiteFull Time
8+ YOEBachelor's degree (or equivalent) with 8+ years experience; ability to obtain Secret clearance; expertise in SystemVerilog/UVM, OVM, VHDL, FPGA/ASIC verification and tools; experience with Mentor Questa or Cadence; strong communication and leadership.
SystemVerilog/UVM, OVM, VHDL, Mentor Questa, Cadence, Perl, Python, C++, Java, Git, Jira, BitBucket, MATLAB, Simulink
1mo
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Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)
San Diego or Nashua or Austin or Totowa or California or New Hampshire or Texas or New Jersey or United States
$130k-$222k/yr OnsiteFull Time
8+ YOEBachelor's degree with 8+ years (or equivalent experience); eligible for Secret clearance; experience with SystemVerilog/UVM/OVM and/or VHDL, Mentor Questa or Cadence tools; FPGA/ASIC verification, test plan development, and strong communication.
SystemVerilog, UVM, OVM, VHDL, Mentor Questa, Cadence, Perl, Python, C++, Java, Git, Jira, BitBucket, Matlab, Simulink
1mo
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Modem HW Design Verification Engineer – AI Driven Next Gen Modem Hardware Development
San Diego or Santa Clara or Boxborough
$128k-$192k/yr OnsiteFull Time
1+ YOEDegree in computer/electrical engineering or related field (BS/MS/PhD) with 1+ years (MS) or 2+ years (BS) engineering experience. Experience in verification planning, SystemVerilog/UVM, RTL languages, C/C++, Python/Perl, Unix/Linux scripting, and GenAI/ML-assisted verification preferred.
SystemVerilog, UVM, OVM, Verilog, VHDL, C, C++, SystemC, Python, Perl, Unix/Linux shell scripting, Makefiles, XML, RTL
1mo
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Design Verification & Test Development Engineer
Bedford, Massachusetts, United States
$64k-$92k/yr OnsiteFull Time
3+ YOE3+ years developing and executing test methods for electromechanical products; BS in Engineering; Python and data analysis (Pandas, NumPy, Matplotlib); experience with test equipment (LabVIEW, PLC, Raspberry Pi, HALT/thermal/vibration chambers); strong communication and problem solving.
Python, Pandas, NumPy, Matplotlib, PLC, Raspberry Pi, LabVIEW, C#, HALT chambers, thermal chambers, vibration tables, power analyzers, pneumatics, oscilloscopes, multi-meters, AI
1w
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Formal Verification Engineer
Boxborough or Austin or Boston or Santa Clara
HybridFull Time
8+ YOE8+ years design verification experience with strong focus on formal verification, proficiency with VC Formal/JasperGold, SVA, formal methods, and scripting (TCL, Python, Perl); Bachelors/Masters in CE/EE.
VC Formal, JasperGold, SystemVerilog Assertions (SVA), TCL, Python, Perl
3mo
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Design Verification Test (DVT) Manager
Derry, New Hampshire, United States
$125k-$140k/yr OnsiteFull Time
5+ YOE3+ MgmtBachelor's in engineering; 5 years product validation/certification; 3+ years management in test/verification; knowledge of safety design/test; experience with certifications (UL) and ISO; create test processes/reports; support factory releases.
1mo
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Mechanical Design Engineer
Hudson, Massachusetts, United States
$80k-$100k/yr OnsiteFull Time
5+ YOEBachelor's in Mechanical Engineering (ABET), 5+ years mechanical design experience, 3+ years SolidWorks, COSMOS experience preferred, heavy-structure and subsystem design, vendor sourcing, verification and validation.
SolidWorks, COSMOS
2w
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MTS, Analog Design Engineer
East Greenwich, Rhode Island, United States
$128k-$219k/yr OnsiteFull Time
onsemi: Designs and manufactures semiconductor solutions for power and sensing.
8+ YOEBS or MS in Electrical Engineering,8+ years mixed-signal design/verification,strong CMOS analog skills,experience with charge pumps,LDOs,gate drivers,debugging silicon,and leading simulations and verification.
Simplis, MATLAB, Cadence Spectre
2mo
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Physical Design Engineer
Westford, Massachusetts, United States
$116k-$219k/yr OnsiteFull Time
3+ YOEBSEE/MSEE or equivalent; 3+ years VLSI physical design on 5/4/3nm; expertise in P&R, timing closure, power/clock distribution, verification; experience with Synopsys/Cadence EDA tools; Python/Perl/Tcl/Make scripting.
ICC2, DC, PT, STAR, ICV, Genus, Innovus, Tempus, Python, Perl, Tcl, Make
1mo
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Engineer: Sr. Electrical Design Engineer
Cambridge, Massachusetts, United States
$80k-$110k/yr OnsiteFull Time
5+ YOEMaster's in EE, 5+ years product development experience, PCB and embedded hardware design, Altium/Eagle, C/Assembly, verification/validation, FDA/ISO 13485 experience, LabVIEW/MATLAB/Simulink familiarity.
Altium, Autodesk Eagle, C, Assembly, Verilog, VHDL, FPGA, ASIC, LabVIEW, MATLAB, Simulink, Java, Android, oscilloscopes, logic analyzers
1w
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Sr. Design Assurance Engineer - Risk Management
Marlborough or Newark
$98k-$153k/yr OnsiteFull Time
Provide design control, risk management, verification/validation, and quality system support for regulated medical devices across the product lifecycle.
1mo
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Principal Engineer Pre-Silicon Digital Verification
Andover or Austin or El Segundo
$146k-$201k/yr OnsiteFull Time
Expertise in ASIC design and digital/mixed-signal verification, System Verilog and UVM, scripting (Unix/Linux shell, Perl, Python), testbench and coverage development, formal verification and analog behavioral modeling.
System Verilog, UVM, Unix/Linux shell, Perl, Python
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