2w
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PHY Design Verification Engineer
San Diego, California, United States
OnsiteFull Time
Work on PHY design verification, emulation, test and validation for wireless SoC development.
1w
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Design Verification Engineer
Aliso Viejo or San Jose or Córdoba or Toronto
OnsiteFull Time
3+ YOEBachelors in EE/CE/CS,3+ years verification experience, SystemVerilog/UVM, coverage-driven verification, C/C++ and scripting (Python,Tcl,Perl),test planning and debug skills.
SystemVerilog, UVM, C, C++, Python, Tcl, Perl
7h
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Design Verification Engineer
San Diego, California, United States
$69k-$116k/yr HybridFull Time
2+ YOEBachelor's in engineering or related field, 2+ years engineering experience, knowledge of ASME Y14.100 and Y14.5 GD&T, PDM experience, strong communication and analytical skills, ability to obtain DoD clearance.
Product Data Management (PDM)
1mo
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Design Verification Engineer
San Diego, California, United States
$81k-$142k/yr OnsiteFull Time
3+ YOEBachelor's in engineering (or equivalent experience); 3+ years engineering experience; strong knowledge of ASME Y14.100 and Y14.5, PDM experience, ability to read/interprete drawings, lead teams, and obtain DoD clearance.
Product Data Management (PDM)
2mo
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Design Verification Engineer - Viasat Government
Marlborough or Carlsbad
$133k-$210k/yr OnsiteFull Time
5+ YOEBachelor's in Electrical or Computer Engineering; 5+ years hardware verification with SystemVerilog/UVM; RTL verification; strong SystemVerilog/UVM; experience with industry EDA tools; US citizenship and active Secret clearance; willingness to travel up to 10%
SystemVerilog, UVM, Siemens Questa, Cadence, Synopsys, Mentor, Python, TCL
1w
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Senior Design Verification Engineer
Mountain View or Hillsboro or Redmond or San Diego
$120k-$235k/yr HybridFull Time
Experience creating emulation/simulation environments, verification using System Verilog/UVM, scripting (Python/Ruby/Perl), Verilog/C/C++, FPGA/emulation experience, and ability to meet export/security screening.
Zebu, Palladium, Verilog, System Verilog, UVM, C, C++, Python, Ruby, Perl, FPGAs, Makefiles
1mo
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GPU Design Verification Engineer
San Diego, California, United States
$180k-$301k/yr OnsiteFull Time
10+ YOEMS/PhD or equivalent,10+ years ASIC design verification experience,SystemVerilog/UVM,constrained random,functional coverage,hw/sw co-simulation,emulation,strong debugging and GPU architecture knowledge.
SystemVerilog, UVM, emulation
1mo
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ASIC Design Verification Engineer
Irvine or Andover or Broomfield
$129k-$207k/yr OnsiteFull Time
3+ YOEConstrained-random design verification experience using System Verilog/UVM, coverage-driven methodologies, experience with VCS/Incisive and scripting (Python/Perl). Degree with significant related experience required (varies by degree).
System Verilog, UVM, VCS, Incisive, Python, Perl
1w
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Design Verification Senior Staff Engineer
Irvine or Santa Clara
$136k-$201k/yr OnsiteFull Time
5+ YOEBachelor's degree in EE/Computer Engineering, 5+ years ASIC/SoC verification experience, strong SystemVerilog/UVM and protocol knowledge, scripting (Python/Perl/Shell), debug and coverage skills.
System Verilog, UVM, Python, Perl, Shell, Palladium, Veloce
2mo
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Principal Design Verification Engineer (Silicon Engineering)
Sunnyvale or Austin or Irvine or Redmond
$210k-$310k/yr OnsiteFull Time
10+ YOEBachelor’s in electrical/computer engineering or computer science; 10+ years in design verification and test bench development.
UVM, OVM, VMM, Python, RTL
2mo
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Satellite Design Verification Engineer, Amazon Leo
Austin or Sunnyvale or Redmond or San Diego
$136k-$184k/yr OnsiteFull Time
5+ YOE2+ years UVM, C, SystemC, and scripting; 5+ years verification for communication systems; Bachelor's degree in Electrical Engineering.
UVM, C, SystemC, DPI-C, SystemVerilog, Matlab
1mo
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Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)
San Diego or Nashua or Austin or Totowa or California or New Hampshire or Texas or New Jersey or United States
$130k-$222k/yr OnsiteFull Time
8+ YOEBachelor's degree with 8+ years (or equivalent experience); eligible for Secret clearance; experience with SystemVerilog/UVM/OVM and/or VHDL, Mentor Questa or Cadence tools; FPGA/ASIC verification, test plan development, and strong communication.
SystemVerilog, UVM, OVM, VHDL, Mentor Questa, Cadence, Perl, Python, C++, Java, Git, Jira, BitBucket, Matlab, Simulink
1w
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Principal Modem PHY IP Design Verification Engineer - Terawave
Texas or California or San Diego
$269k-$377k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
10+ YOEBachelor's in EE/CE/CS,10+ years verification experience, SystemVerilog and UVM expertise, modem PHY/DSP familiarity, scripting with Python/Perl/shell, strong RTL/testbench debugging, ability to work with cross-functional teams.
SystemVerilog, UVM, Python, Perl, shell, MATLAB, C/C++
3w
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Sr. Principal Digital Design Verification Lead
San Diego, California, United States
$142k-$213k/yr HybridFull Time
5+ YOE5+ years FPGA verification experience, strong SystemVerilog/UVM skills, Questa/ModelSim experience, RTL knowledge (Verilog/VHDL), scripting (Python/Tcl/Bash), Git, and ability to obtain US Secret clearance and Program Access.
SystemVerilog, UVM, Questa, ModelSim, Verilog, VHDL, SVA, Python, Tcl, Bash, Git
1mo
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Sr. Principal AMS Verification Engineer (Irvine, CA, US)
Irvine, California, United States
$143k-$286k/yr OnsiteFull Time
8+ YOERequires BS+15 yrs (MS+12 or PhD+8) experience; strong AMS design/verification background, Verilog-A and SystemVerilog RNM modeling, Cadence Virtuoso/ADS experience, Python scripting, leadership and communication skills.
Cadence Virtuoso, ADS, Verilog-A, SystemVerilog, SystemVerilog Real Number Modeling (RNM), Python
1mo
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Physical Design Engineer
San Jose or Irvine
$150k-$250k/yr OnsiteFull Time
5+ YOEBachelor's/Master's in EE, 5+ years full-chip physical verification experience, multiple tapeouts, hands-on with ICV or Calibre, ability to assemble PV flow and floorplanning expertise; Tcl/Python/shell automation preferred.
ICV, Calibre, Tcl, Python, Shell
3w
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Design Quality Engineer
Irvine, California, United States
$105k-$135k/yr OnsiteFull Time
5+ YOEBS in technical or life science,5+ years in medical device quality systems (ISO 13485,21 CFR 820),strong technical writing,test planning,verification/validation experience,MS Office proficiency,and ability to travel up to 90 days/yr.
Microsoft Office
2mo
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Staff FPGA Design Engineer
Irvine, California, United States
$150k-$190k/yr OnsiteFull Time
8+ YOEBachelor's in EE/CE, 8+ years FPGA RTL architecture/development/verification, strong SystemVerilog or VHDL skills, experience with Microship Polarfire/AMD Zynq/Versal/Ultrascale, verification methodologies, Git, Python/Tcl/Bash, C/C++ on Linux, and eligibility for DoD security clearance.
SystemVerilog, VHDL, Microship Polarfire, AMD Zynq US+, Versal, AMD Ultrascale, Vivado, Mentor Modelsim/Questasim, AXI, PCIe, DDR4, DDR5, JESD204B, JESD204C, 100Gb ethernet, SPI, I2C, UART, CAN FD, LVDS, Git, Python, Tcl, Bash, Linux, C/C++
2mo
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Senior Principal Engineer Digital ASIC Design/Manager
San Diego, California, United States
$214k-$348k/yr OnsiteFull Time
15+ YOEBS or MS in Electrical Engineering; 15 years in Digital ASIC design; leadership; cross-functional collaboration; RTL/verification; experience with mixed-signal interfaces is a plus.
Verilog, SystemVerilog, LINT, LEC, RDC/CDC, SDF, Genus, Conformal, Innovus, Spyglass Lint, TetraMax, Xcelium, Cadence, Synopsys PrimeTime, VCS, UGV, UVM
1w
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Sr. Software Design Assurance Engineer
Colorado Springs or San Diego or Plymouth
$80k-$136k/yr HybridFull Time
8+ YOE8+ years in medical device software quality or development; expertise in software design verification, risk management (IEC 62304, ISO 14971), and regulatory standards (21 CFR 820, ISO 13485); BS/MS in engineering field; experience with Agile/SAFe and defect/traceability tools.
Agile, SAFe, Jira, ClearQuest, JMP, Minitab, JAMA, IBM DOORS
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