112 design verification engineer jobs at 32 companies in Newman, CA
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Design Verification Engineer
San Jose, California, United States
$144k-$230k/yr OnsiteFull Time
12+ YOEBachelor's in EE/electronic engineering or CS required; 12+ years experience; strong System Verilog, UVM/OVM, RTL, C/C++, Perl, SystemC skills; ASIC design verification, debugging, and coverage experience; US work authorization required.
System Verilog, UVM, OVM, RTL, C/C++, Perl, SystemC, Emulators, FPGA
3w
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Design Verification Engineer
Aliso Viejo or San Jose or Córdoba or Toronto
OnsiteFull Time
3+ YOEBachelors in EE/CE/CS,3+ years verification experience, SystemVerilog/UVM, coverage-driven verification, C/C++ and scripting (Python,Tcl,Perl),test planning and debug skills.
SystemVerilog, UVM, C, C++, Python, Tcl, Perl
2w
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SoC Design Verification Engineer
San Jose, California, United States
$124k-$213k/yr HybridFull Time
Experience in SoC/CPU verification, testbench development, and verification metrics; strong coding in Verilog/System Verilog, UVM, C/C++, scripting (Perl/Python); Bachelors/Masters in computer or electrical engineering.
Verilog, System Verilog, UVM, C, C++, Perl, Python
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Design Verification Engineer IV
San Jose, California, United States
$112k-$176k/yr OnsiteFull Time
6+ YOEExpertise in SystemVerilog/UVM, AXI/PCIe/Ethernet/NOC/UCIe protocols, CPU architectures (ARM, RISC-V) and C/C++; 6–8+ years verification experience; formal verification and scripting experience; ability to architect SoC verification environments.
SystemVerilog (SV), UVM, AXI, NOC, Ethernet, PCIe, UCIe, ARM, RISC-V, C, C++
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Senior Design Verification Engineer
Tempe or Independence or Arizona or Ohio or San Jose or New York City
$142k-$224k/yr HybridFull Time
8+ YOE8+ years design verification experience with UVM and testbench development; Bachelor's in EE/CE or related; experience with Questa/Xcelium/VCS; AI/agentic DV experience preferred; US citizenship and ability to obtain Secret clearance; travel up to 10%.
UVM, SystemVerilog, VHDL, Verilog, Questa, Xcelium, VCS, Jira
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Director, Design Verification
San Jose, California, United States
$219k-$351k/yr OnsiteFull Time
15+ YOEBE/MS in Computer/Electrical Engineering or Computer Science; 15+ years ASIC verification; leadership in verification; multiple tape-outs; UVM, C++, SystemVerilog; strong communication and collaborative skills.
UVM, C++, SystemVerilog, verification tools
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Principal Engineer, ASIC Design Verification
San Jose, California, United States
$190k-$240k/yr OnsiteFull Time
12+ YOEMS in Electrical or Computer Engineering; 12+ years ASIC/SoC verification experience; SystemVerilog and UVM expert; verification environment design; scripting for automation.
SystemVerilog, UVM, Scripting (Python, Perl, Tcl, Shell)
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Sr. Design Verification Engineer
San Jose, California, United States
$130k-$160k/yr OnsiteFull Time
7+ YOEBS/MS in EE/CE, 7+ years RTL/functional verification using SV/UVM, PCIe and gate-level experience, firmware-based simulation and C knowledge, strong debugging and scripting (Python/Perl/Shell) skills.
SV, UVM, C, Python, Perl, Shell scripting, PILOT
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Principal Design Verification Engineer- SerDes/PHY
San Jose, California, United States
$207k-$230k/yr OnsiteFull Time
8+ YOEBachelor's degree in engineering and 8+ years of high-speed SerDes, PHY, or mixed-signal design verification experience. Requires SystemVerilog, UVM, analog/mixed-signal co-simulation, RNM, and serial protocol expertise.
SystemVerilog, UVM, Python, Perl, Palladium, Veloce, ZeBu, CXL, Ethernet, NVLink, PCIe, UALink, UCIe
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ASIC Design Verification Engineer
San Jose, California, United States
$165k-$241k/yr OnsiteFull Time
7+ YOEBachelor’s +7 years, or Master’s +4, or PhD +1; SystemVerilog/UVM; verification methodologies incl. emulation; architecture and leadership in verification; scripting (Python, Perl) and C/C++.
SystemVerilog, UVM, emulation, Python, Perl, C/C++
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Principal Engineer, Design Verification - DDR Memory Subsystems
San Jose, California, United States
$210k-$299k/yr OnsiteFull Time
15+ YOEBachelor's in EE/CE/CS, 15+ years design verification experience, 10+ years DDR subsystem verification, expertise in SystemVerilog/UVM/SVA, constrained-random verification, functional coverage, debugging with simulators and protocol analyzers, and leadership of verification programs.
SystemVerilog, UVM, SystemVerilog Assertions (SVA), Python, Perl, Tcl, Shell, CI/CD
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SoC Physical Design Verification Engineer
San Jose, California, United States
OnsiteFull Time
Experience in physical verification of system-on-chip (SoC) designs and semiconductor implementation; ability to craft solutions for high-performance, power-efficient processors.
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Senior Staff Engineer, GPU Design Verification (Formal Verification)
San Jose, California, United States
$198k-$297k/yr OnsiteFull Time
8+ YOE8+ years verification experience (formal verification focus), proficiency in formal methods, System Verilog/SVA, Python/Perl/C++, EDA formal tools, strong debugging and architecture knowledge; BS/MS/PhD in CS/CE/related.
Python, Perl, C/C++, System Verilog, System Verilog Assertions (SVA), Confluence, JIRA, Universal Verification Methodology (UVM), UPF
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Design Verification Architect
San Jose or United States
$150k-$300k/yr HybridFull Time
12+ YOEBachelor's/Master's in EE/CE, 12+ years design verification experience for large SoCs, expertise in SystemVerilog, UVM, Portable Stimulus (PSS), coverage-driven and assertion-based verification, and strong architecture and debugging skills.
SystemVerilog, UVM, Portable Stimulus (PSS), PCIe, DDR, Ethernet, CXL, UCIe
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Staff Design Verification Engineer – SoC and eFPGA
San Jose, California, United States
$151k-$219k/yr OnsiteFull Time
5+ YOEMaster's degree or equivalent experience; expertise in SoC verification, UVM, SystemVerilog, Verilog, C/C++, Python, RTL debugging, bus protocols, automation, and distributed compute environments.
UVM, SystemVerilog, Verilog, C, C++, Python, SystemC, Transaction-Level Modeling (TLM), AXI, AHB, RTL, FPGA, SoC
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Staff/Principal Engineer - Design Verification (SoC expert/lead)
San Jose, California, United States
$168k-$336k/yr OnsiteFull Time
10+ YOEBachelor's in EE/CS or equivalent, 10+ years SoC verification experience, expert SystemVerilog and UVM, experience developing SoC test plans, emulation exposure, and leadership in complex verification programs.
SystemVerilog, UVM, Gen-AI
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Principal Engineer, AI & ML Design Verification (AI2517)
San Jose, California, United States
$204k-$316k/yr OnsiteFull Time
12+ YOEBS/MS in EE or CS required, 12+ years verification experience with UVM and System Verilog, AMBA knowledge, testbench and coverage development, silicon/emulation debug, strong debugging and problem-solving skills.
UVM, System Verilog, System Verilog Assertion (SVA), AMBA
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Advanced Physical Design and Verification Engineer (7036)
San Jose or California
$86k-$134k/yr HybridFull Time
Master’s degree in Electrical Engineering or Computer Science; knowledge of VLSI and physical design; research or internship experience; EDA tools; Python, Perl, or TCL programming; regular customer-site work.
Python, Perl, TCL, EDA, DRC, LVS, ERC, ANTENNA, EMIR, Netlist-GDS, P&R
3w
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Verification CAD Engineer
Milpitas, California, United States
$160k-$265k/yr HybridFull Time
7+ YOEB.S./M.S. in EE/CE/CS,7+ years design verification experience,expert SystemVerilog/UVM and SVA/CDV,advanced Python and Shell skills,Linux and regression farm experience (LSF/NC/Slurm),familiarity with Cadence verification tools.
SystemVerilog, UVM, SVA, Python, Shell, Perl, Xcelium, SimVision, vManager, Verissium, Linux, LSF, NC, Slurm
2mo
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Design Verification Technical Architect
Austin or San Jose or Santa Clara
$150k-$190k/yr OnsiteFull Time
10+ YOE10+ years DV experience; SV-UVM; Python; Verilog; C; high speed protocol (PCIe, UCIe, LPDDR5, Ethernet200G); SS/SOC level verification; source control (git); emulation; Arm core; C-base; test plan development.
SV-UVM, Python, Verilog, C, PCIe, UCIe, LPDDR5, Ethernet200G+, SystemVerilog, RISCV, AMBA, git, Emulation, Arm Core, C-Base
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