93 design verification engineer jobs at 44 companies in Salem, NH
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Staff Engineer, Design Verification Engineering
Wilmington, Massachusetts, United States
$172k-$210k/yr HybridFull Time
4+ YOEMaster's+4yrs or Bachelor's+6yrs in relevant engineering; experience with System Verilog and UVM, metric-driven verification, simulation debug, IP/VIP integration, verification planning, and scripting for automation.
UVM, System Verilog
3mo
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Design Verification Engineer - Viasat Government
Marlborough or Carlsbad
$133k-$210k/yr OnsiteFull Time
5+ YOEBachelor's in Electrical or Computer Engineering; 5+ years hardware verification with SystemVerilog/UVM; RTL verification; strong SystemVerilog/UVM; experience with industry EDA tools; US citizenship and active Secret clearance; willingness to travel up to 10%
SystemVerilog, UVM, Siemens Questa, Cadence, Synopsys, Mentor, Python, TCL
2mo
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ASIC Design Verification Engineer
Irvine or Andover or Broomfield
$129k-$207k/yr OnsiteFull Time
3+ YOEConstrained-random design verification experience using System Verilog/UVM, coverage-driven methodologies, experience with VCS/Incisive and scripting (Python/Perl). Degree with significant related experience required (varies by degree).
System Verilog, UVM, VCS, Incisive, Python, Perl
2w
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Design Verification Engineer
Waltham, Massachusetts, United States
OnsiteFull Time
Responsible for verifying the functionality and performance of Apple's system-on-chip products; the posting does not specify education, certifications, or experience requirements.
1mo
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Senior Staff Engineer, Design Verification
Westborough, Massachusetts, United States
$151k-$223k/yr OnsiteFull Time
3+ YOEBachelor's with 5+ years or Master's/PhD with 3+ years in digital design/verification; expertise in UVM, constrained-random verification, SVA, RTL debug; C/C++ and scripting (Python/Perl); Linux experience.
UVM, SystemVerilog, SystemVerilog Assertions (SVA), C, C++, Python, Perl, Linux
3mo
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Design Verification Engineer - Viasat Government
Marlborough or Carlsbad
$133k-$210k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE or related,5+ years hardware verification experience with SystemVerilog/UVM,experience with industry EDA tools,US citizenship and active Secret clearance required,ability to travel up to 10%.
SystemVerilog, UVM, Siemens Questa, Cadence, Synopsys, Mentor, AMD/Xilinx Vivado, Altera Quartus, Microchip Libero, TCL, Perl, Python, Linux
2w
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SOC Design Verification Lead
Boxborough, Massachusetts, United States
$175k-$300k/yr HybridFull Time
5+ YOESeasoned SoC design verification and infrastructure architect with testbench architecture, verification methodology, project execution, and SoC architecture expertise; UVM, C++, SystemVerilog, GitHub Copilot, and Cursor experience preferred.
UVM, C++, SystemVerilog, GitHub Copilot, Cursor
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Design Verification Engineer, PLM
Portsmouth, New Hampshire, United States
OnsiteFull Time
2+ YOEBachelor's in engineering and 2+ years experience in design, development, and testing; knowledge of design control, validation, and regulatory standards; proficiency with test documentation and engineering change processes.
Azure DevOps, JIRA, Greenlight Guru, SAP
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Senior Staff Design Verification Engineer – Coherent Interconnect
Boston or Austin
OnsiteFull Time
8+ YOE8+ years ASIC/SoC design verification experience, strong SystemVerilog and Python skills, deep knowledge of cache-coherent interconnects and protocols (CHI, ACE, CXL, AXI), BS/MS in EE/CE/CS, strong communication and leadership.
SystemVerilog, Python
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Design Verification Engineer – Physical AI Compute
Santa Clara or Austin or Boston
$75k-$275k/yr OnsiteFull Time
Experience verifying complex digital/SoC systems with SystemVerilog/UVM, C/C++, assertions, formal, emulation and debugging across HW/SW boundaries.
SystemVerilog, UVM, C, C++, formal verification, emulation, FPGA
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Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)
San Diego or Nashua or Austin or Totowa or California or New Hampshire or Texas or New Jersey or United States
$130k-$222k/yr OnsiteFull Time
8+ YOEBachelor's degree with 8+ years (or equivalent experience); eligible for Secret clearance; experience with SystemVerilog/UVM/OVM and/or VHDL, Mentor Questa or Cadence tools; FPGA/ASIC verification, test plan development, and strong communication.
SystemVerilog, UVM, OVM, VHDL, Mentor Questa, Cadence, Perl, Python, C++, Java, Git, Jira, BitBucket, Matlab, Simulink
3mo
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Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)
Nashua or Manchester or Largo or New Hampshire or Florida or United States
$130k-$222k/yr OnsiteFull Time
8+ YOEBachelor's degree (or equivalent) with 8+ years experience; ability to obtain Secret clearance; expertise in SystemVerilog/UVM, OVM, VHDL, FPGA/ASIC verification and tools; experience with Mentor Questa or Cadence; strong communication and leadership.
SystemVerilog/UVM, OVM, VHDL, Mentor Questa, Cadence, Perl, Python, C++, Java, Git, Jira, BitBucket, MATLAB, Simulink
3d
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Sr. Engineer, SoC Design Verification Engineer, System Management Controller
Boston or Santa Clara or Toronto
$100k-$500k/yr HybridFull Time
Proficiency in SystemVerilog, SV-UVM, Python, and C/C++; experience with test plans, verification infrastructure, hardware/software debugging, and distributed collaboration.
SystemVerilog, SV-UVM, Python, C, C++, Copilot, Cursor, Claude, UCIe, BoW, Cocotb
3mo
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Design Verification Test (DVT) Manager
Derry, New Hampshire, United States
$125k-$140k/yr OnsiteFull Time
5+ YOE3+ MgmtBachelor's in engineering; 5 years product validation/certification; 3+ years management in test/verification; knowledge of safety design/test; experience with certifications (UL) and ISO; create test processes/reports; support factory releases.
2mo
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Mechanical Design Engineer
Hudson, Massachusetts, United States
$80k-$100k/yr OnsiteFull Time
5+ YOEBachelor's in Mechanical Engineering (ABET), 5+ years mechanical design experience, 3+ years SolidWorks, COSMOS experience preferred, heavy-structure and subsystem design, vendor sourcing, verification and validation.
SolidWorks, COSMOS
2w
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Senior ASIC Design Verification Infrastructure and Tools Engineer – GPU
Santa Clara or Austin or Westford or Durham or California
$136k-$265k/yr HybridFull Time
5+ YOEBS/MS in electrical engineering, computer engineering, or computer science; 5+ years of relevant experience; ASIC workflows, UVM, Verilog/SystemVerilog, simulation tools, scripting, and root-cause analysis skills.
UVM, Verilog, SystemVerilog, VCS, Verdi, Xcelium, Python, Perl
4d
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Sr. ASIC Verification Engineer (TERADYNE, North Reading, MA)
North Reading, Massachusetts, United States
$155k-$308k/yr OnsiteFull Time
8+ YOEBachelor’s degree in a relevant technical field and 8+ years of ASIC/SoC verification experience. Requires SystemVerilog, UVM, SystemC, C++, OOP, scripting, EDA tools, and complex digital design verification expertise.
SystemVerilog, UVM, SystemC, C++, Python, Perl
2w
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Senior ASIC Design Verification Infrastructure and Tools Engineer – GPU
Santa Clara or Austin or Westford or Durham or California
$136k-$265k/yr HybridFull Time
5+ YOEBachelor's or master's degree in engineering or computer science, 5+ years' experience, ASIC workflows, UVM, Verilog/SystemVerilog, simulation tools, and Python, Perl, or systems programming.
Python, Perl, Verilog, SystemVerilog, UVM, VCS, Verdi, Xcelium
1w
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Senior Software Verification Engineer
Burlington, Massachusetts, United States
$78k-$156k/yr OnsiteFull Time
5+ YOERequires 5+ years of regulated medical-device software verification experience, IEC 62304 and FDA design-control knowledge, strong communication, and onsite hardware-testing availability.
Squish, Appium, XCUITest, Espresso, Python, Java, C, C++, iOS, Android, BLE, Wi-Fi, Cellular, NFC
1w
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Senior Software Verification Engineer
Burlington, Massachusetts, United States
$78k-$156k/yr OnsiteFull Time
5+ YOERequires 5+ years of software verification experience in medical devices or regulated industries, IEC 62304 and FDA design control knowledge, and strong communication skills. Python and mobile or embedded testing experience preferred.
Squish, Appium, XCUITest, Espresso, Python, Java, C, C++, iOS, Android, BLE, Wi-Fi, Cellular, NFC, IEC 62304, ISO 13485, FDA
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