71 design verification engineer jobs at 34 companies in Smithfield, RI
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Staff Engineer, Design Verification Engineering
Wilmington, Massachusetts, United States
$172k-$210k/yr HybridFull Time
4+ YOEMaster's+4yrs or Bachelor's+6yrs in relevant engineering; experience with System Verilog and UVM, metric-driven verification, simulation debug, IP/VIP integration, verification planning, and scripting for automation.
UVM, System Verilog
2mo
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Design Verification Engineer - Viasat Government
Marlborough or Carlsbad
$133k-$210k/yr OnsiteFull Time
5+ YOEBachelor's in Electrical or Computer Engineering; 5+ years hardware verification with SystemVerilog/UVM; RTL verification; strong SystemVerilog/UVM; experience with industry EDA tools; US citizenship and active Secret clearance; willingness to travel up to 10%
SystemVerilog, UVM, Siemens Questa, Cadence, Synopsys, Mentor, Python, TCL
1d
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Design Verification Engineer
Waltham, Massachusetts, United States
OnsiteFull Time
Responsible for verifying the functionality and performance of Apple's system-on-chip products; the posting does not specify education, certifications, or experience requirements.
3w
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Senior Staff Engineer, Design Verification
Westborough, Massachusetts, United States
$151k-$223k/yr OnsiteFull Time
3+ YOEBachelor's with 5+ years or Master's/PhD with 3+ years in digital design/verification; expertise in UVM, constrained-random verification, SVA, RTL debug; C/C++ and scripting (Python/Perl); Linux experience.
UVM, SystemVerilog, SystemVerilog Assertions (SVA), C, C++, Python, Perl, Linux
2mo
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Design Verification Engineer - Viasat Government
Marlborough or Carlsbad
$133k-$210k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE or related,5+ years hardware verification experience with SystemVerilog/UVM,experience with industry EDA tools,US citizenship and active Secret clearance required,ability to travel up to 10%.
SystemVerilog, UVM, Siemens Questa, Cadence, Synopsys, Mentor, AMD/Xilinx Vivado, Altera Quartus, Microchip Libero, TCL, Perl, Python, Linux
1mo
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Senior Staff Design Verification Engineer – Coherent Interconnect
Boston or Austin
OnsiteFull Time
8+ YOE8+ years ASIC/SoC design verification experience, strong SystemVerilog and Python skills, deep knowledge of cache-coherent interconnects and protocols (CHI, ACE, CXL, AXI), BS/MS in EE/CE/CS, strong communication and leadership.
SystemVerilog, Python
4w
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Design Verification Engineer – Physical AI Compute
Santa Clara or Austin or Boston
$75k-$275k/yr OnsiteFull Time
Experience verifying complex digital/SoC systems with SystemVerilog/UVM, C/C++, assertions, formal, emulation and debugging across HW/SW boundaries.
SystemVerilog, UVM, C, C++, formal verification, emulation, FPGA
13h
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Formal Verification Engineer
Austin or Boston or Santa Clara
$127k-$217k/yr HybridFull Time
8+ YOERequires 8+ years in design verification focused on formal verification, VC Formal or JasperGold, SystemVerilog Assertions, TCL/Python/Perl, and a bachelor's or master's degree in computer or electrical engineering.
VC Formal, JasperGold, SystemVerilog Assertions (SVA), TCL, Python, Perl
2mo
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Modem HW Design Verification Engineer – AI Driven Next Gen Modem Hardware Development
San Diego or Santa Clara or Boxborough
$128k-$192k/yr OnsiteFull Time
1+ YOEDegree in computer/electrical engineering or related field (BS/MS/PhD) with 1+ years (MS) or 2+ years (BS) engineering experience. Experience in verification planning, SystemVerilog/UVM, RTL languages, C/C++, Python/Perl, Unix/Linux scripting, and GenAI/ML-assisted verification preferred.
SystemVerilog, UVM, OVM, Verilog, VHDL, C, C++, SystemC, Python, Perl, Unix/Linux shell scripting, Makefiles, XML, RTL
2mo
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Mechanical Design Engineer
Hudson, Massachusetts, United States
$80k-$100k/yr OnsiteFull Time
5+ YOEBachelor's in Mechanical Engineering (ABET), 5+ years mechanical design experience, 3+ years SolidWorks, COSMOS experience preferred, heavy-structure and subsystem design, vendor sourcing, verification and validation.
SolidWorks, COSMOS
4w
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MTS, Analog Design Engineer
East Greenwich, Rhode Island, United States
$128k-$219k/yr OnsiteFull Time
onsemi: Designs and manufactures semiconductor solutions for power and sensing.
8+ YOEBS or MS in Electrical Engineering,8+ years mixed-signal design/verification,strong CMOS analog skills,experience with charge pumps,LDOs,gate drivers,debugging silicon,and leading simulations and verification.
Simplis, MATLAB, Cadence Spectre
1d
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Senior ASIC Design Verification Infrastructure and Tools Engineer – GPU
Santa Clara or Austin or Westford or Durham or California
$136k-$265k/yr HybridFull Time
5+ YOEBachelor's or master's degree in engineering or computer science, 5+ years' experience, ASIC workflows, UVM, Verilog/SystemVerilog, simulation tools, and Python, Perl, or systems programming.
Python, Perl, Verilog, SystemVerilog, UVM, VCS, Verdi, Xcelium
1d
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Senior ASIC Design Verification Infrastructure and Tools Engineer – GPU
Santa Clara or Westford or Austin or Durham or California
$136k-$265k/yr OnsiteFull Time
5+ YOEBS/MS or equivalent experience; 5+ years relevant experience; ASIC workflows, UVM, Verilog/SystemVerilog, simulation/debug tools, Python or Perl, and root-cause analysis skills required.
UVM, Verilog, SystemVerilog, VCS, Verdi, Xcelium, Python, Perl
2w
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Principal RFIC Design Engineer
Chelmsford, Massachusetts, United States
$148k-$193k/yr OnsiteFull Time
5+ YOEMSEE or PhD and 5–10+ years of IC design experience, with expertise in RF/mixed-signal, analog, microwave/mmWave circuits, simulation, EM analysis, verification, and silicon characterization.
ADS, Cadence, HFSS, EMX, Verilog, VerilogA
1mo
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Engineer: Sr. Electrical Design Engineer
Cambridge, Massachusetts, United States
$80k-$110k/yr OnsiteFull Time
5+ YOEMaster's in EE, 5+ years product development experience, PCB and embedded hardware design, Altium/Eagle, C/Assembly, verification/validation, FDA/ISO 13485 experience, LabVIEW/MATLAB/Simulink familiarity.
Altium, Autodesk Eagle, C, Assembly, Verilog, VHDL, FPGA, ASIC, LabVIEW, MATLAB, Simulink, Java, Android, oscilloscopes, logic analyzers
2w
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Sr. Design Assurance Engineer - Risk Management
Marlborough or Newark
$98k-$153k/yr OnsiteFull Time
Provide design control, risk management, verification/validation, and quality system support for regulated medical devices across the product lifecycle.
2d
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Principal Electrical Engineer - FPGA Verification
Tewksbury or Marlborough
$108k-$205k/yr OnsiteFull Time
8+ YOESTEM degree and 8+ years of relevant experience required. Requires FPGA verification, SystemVerilog, UVM, digital design verification, protocols, simulators, version control, and active DoD Secret clearance.
SystemVerilog, UVM, AXI, PCIe, Ethernet, DDR, Questa, VCS, Xcelium, Git, ClearCase, SVN, UVMF, Vivado, Quartus, Python, Tcl, Perl, VHDL, SLURM
1mo
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Engineer Sr., Systems
Buffalo or East Aurora or Cambridge
$110k-$150k/yr OnsiteFull Time
5+ YOEBachelor's in engineering, 5+ years systems/design engineering experience, ability to obtain US security clearance, ~50% travel, proficiency with requirements management and verification/validation, DOORS experience.
Dynamic Object-Oriented Requirements System (DOORS)
1d
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Electrical Engineer
North Kingstown, Rhode Island, United States
OnsiteFull Time
8+ YOEBachelor's degree in Electrical Engineering and 8–10+ years of electrical design and product development experience. Requires schematic capture, PCB, embedded systems, wireless protocols, circuit verification, and testing expertise.
Altium, KiCad, Eagle, Wi-Fi, BLE, Zigbee, LTSpice, Saber, Mathcad, Maple, oscilloscopes, spectrum analyzers, power analyzers, timing analyzers, PCB
1w
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Senior Product Integrity Engineer
Needham, Massachusetts, United States
$60k-$110k/yr OnsiteFull Time
3+ YOEBachelor's in engineering or related,3+ years in design verification/validation,experience with DFMEA,DVP&R,ECN management,analytical and communication skills.
Microsoft Word, Microsoft Excel, Microsoft PowerPoint, SharePoint
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