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Design Verification Engineer
San Jose, California, United States
$144k-$230k/yr OnsiteFull Time
12+ YOEBachelor's in EE/electronic engineering or CS required; 12+ years experience; strong System Verilog, UVM/OVM, RTL, C/C++, Perl, SystemC skills; ASIC design verification, debugging, and coverage experience; US work authorization required.
System Verilog, UVM, OVM, RTL, C/C++, Perl, SystemC, Emulators, FPGA
2mo
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Design Verification Engineer
Sunnyvale, California, United States
$190k-$230k/yr OnsiteFull Time
3+ YOE3+ years design verification experience; deep knowledge of SystemVerilog, DPI, UVM; strong programming (object-oriented) skills; experience with testbenches, simulation, emulation, and silicon bring-up.
SystemVerilog, DPI, UVM, Python, Perl
2mo
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Design Verification Engineer
Santa Clara, California, United States
$146k-$250k/yr OnsiteFull Time
SystemVerilog/UVM verification expertise; IP/subsystem/SoC verification; testbench development; strong debugging and collaboration.
SystemVerilog, UVM, VCS, Verdi/DVE, Python, Shell, Tcl, Make
2w
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Design Verification Engineer
Mountain View, California, United States
$120k-$475k/yr HybridFull Time
Concept-to-silicon verification experience with SystemVerilog, UVM, ABV, and scripting; production verification and silicon bring-up experience preferred.
SystemVerilog, Python, C/C++, Bluespec, UVM, assertion-based verification (ABV)
1w
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Design Verification Engineer
Aliso Viejo or San Jose or Córdoba or Toronto
OnsiteFull Time
3+ YOEBachelors in EE/CE/CS,3+ years verification experience, SystemVerilog/UVM, coverage-driven verification, C/C++ and scripting (Python,Tcl,Perl),test planning and debug skills.
SystemVerilog, UVM, C, C++, Python, Tcl, Perl
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Staff Engineer, Design Verification
Santa Clara, California, United States
$114k-$171k/yr OnsiteFull Time
3+ YOEBachelor's in Computer/Electrical Engineering + 3+ years (2+ with MS/PhD); System Verilog/UVM, verification test-plan development, verification tools, C/C++, Python/Perl, and Linux proficiency.
System Verilog/UVM, C/C++, Python, Perl, Linux, CXL, PCIE, Ethernet, ARM
3d
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C - Focused Design Verification Engineer
Sunnyvale, California, United States
OnsiteFull Time
Experience in design verification for wireless systems-on-chip, including RTL, emulation, and verification methodologies.
1mo
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Design Verification Engineer
Santa Clara, California, United States
$142k-$200k/yr HybridFull Time
3+ YOEBS/MS in EE/CS (3+ years DV), hands-on coding in SystemVerilog, C, C++, Python, experience with UVM/ABV and simulation/formal verification, familiarity with interconnect protocols and AI-assisted development tools.
SystemVerilog, C, C++, Python, UVM, ABV, JasperGold, VC Formal, AI-assisted development tools, emulation, FPGA
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Design Verification Engineer IV
San Jose, California, United States
$112k-$176k/yr OnsiteFull Time
6+ YOEExpertise in SystemVerilog/UVM, AXI/PCIe/Ethernet/NOC/UCIe protocols, CPU architectures (ARM, RISC-V) and C/C++; 6–8+ years verification experience; formal verification and scripting experience; ability to architect SoC verification environments.
SystemVerilog (SV), UVM, AXI, NOC, Ethernet, PCIe, UCIe, ARM, RISC-V, C, C++
1mo
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Senior Design Verification Engineer
Tempe or Independence or Arizona or Ohio or San Jose or New York City
$142k-$224k/yr HybridFull Time
8+ YOE8+ years design verification experience with UVM and testbench development; Bachelor's in EE/CE or related; experience with Questa/Xcelium/VCS; AI/agentic DV experience preferred; US citizenship and ability to obtain Secret clearance; travel up to 10%.
UVM, SystemVerilog, VHDL, Verilog, Questa, Xcelium, VCS, Jira
2w
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Senior Design Verification Engineer
Sunnyvale, California, United States
$154k-$311k/yr HybridFull Time
5+ YOEDevelop and execute verification plans using SystemVerilog/UVM and emulation platforms; 5+ years verification experience; bachelor\u0002s in EE/CE/CS; strong debugging, scripting, and coverage skills.
SystemVerilog, UVM, Cadence Palladium, Synopsys ZeBu, Mentor Veloce, Python, Perl, TCL, JasperGold, VC Formal
4w
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ASIC Engineer, Design Verification
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
6+ YOEBachelor's in CS/CE or equivalent; 6+ years SystemVerilog/UVM or C/C++ verification and IP/SoC level verification experience; EDA tools and scripting (Python, TCL, Perl, Shell).
SystemVerilog, UVM, C, C++, Python, TCL, Perl, Shell, Mercurial, Hg, Git, SVN, SV Assertions, Formal, Emulation, PCIe, RoCE, DDR, HBM, Ethernet
2w
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Senior Design Verification Engineer
Sunnyvale, California, United States
$154k-$311k/yr HybridFull Time
5+ YOE5+ years verification experience, Bachelor in EE/CE/CS, strong SystemVerilog/UVM skills, emulation platform experience, scripting (Python/Perl/TCL), debug and coverage-driven verification expertise.
SystemVerilog, UVM, Cadence Palladium, Synopsys ZeBu, Mentor Veloce, Python, Perl, TCL, JasperGold, VC Formal, UPF, CPF, FPGA
2mo
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Design Verification (DV) Engineer
Mountain View or Austin
$200k-$320k/yr OnsiteFull Time
Expert SystemVerilog and UVM verification skills; hands-on experience with logic simulators and waveform debuggers; coverage-driven verification, assertion and regression infrastructure experience; optional formal, Python/Tcl scripting, and RISC-V familiarity.
SystemVerilog, UVM, Synopsys VCS, Cadence Xcelium, Synopsys Verdi, Cadence SimVision, Python, Tcl, LLVM, RISC-V
1mo
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CPU Design Verification Engineer
Mountain View, California, United States
$138k-$198k/yr OnsiteFull Time
3+ YOEBachelor's in EE/CE/CS (or equivalent), 3+ years verification experience with UVM/SystemVerilog, B.S. required; preferred MS/PhD, low-power verification, scripting (Python/Perl/Shell/Bash), ARM ISA, and Linux/Android knowledge.
Universal Verification Methodology (UVM), SystemVerilog, Python, Perl, Shell, Bash, Advanced RISC Machine (ARM), Linux, Android
2w
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Formal Design Verification Engineer
Raleigh or Austin or Hillsboro or Mountain View or Redmond
$120k-$235k/yr HybridFull Time
1+ YOEDegree in EE/CS or equivalent plus technical engineering experience; formal verification, protocol and IP verification experience; ability to pass Microsoft Cloud Background Check and export-control screening.
Coherent Hub Interface (CHI), Advanced Microcontroller Bus Architecture (AMBA), PCIe, CXL, Universal Verification Methodology (UVM), System Verilog Test Bench (SVTB), Python
1mo
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Design Verification Engineer, Principal
Santa Clara, California, United States
$159k-$238k/yr OnsiteFull Time
5+ YOEBS in CE/EE/CS with 10+ years (or MS/PhD with 5+ years) verification and firmware/software experience; expertise in System Verilog, UVM, random verification, Python/Perl, EDA tools, OOD, Linux, C++ and ARM assembly; leadership and tape-out experience.
System Verilog, UVM, Python, Perl, EDA Verification tools, Linux, C++, ARM assembly
1d
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ASIC Design Verification Engineer
San Jose, California, United States
$155k-$223k/yr OnsiteFull Time
3+ YOEBachelor's/Master's/PhD in electrical/computer engineering or related, 3+–5+ years verification experience, System Verilog and UVM, ASIC verification and debugging skills, emulation/post-silicon and networking experience preferred.
System Verilog, UVM, Linux, C, C++, Python, Perl, Emulation, Formal verification
1mo
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Design and Verification Engineer
San Jose, California, United States
$150k-$350k/yr OnsiteFull Time
Degree in EE/CE or related, experience in RTL design and functional verification, proficiency with Verilog/SystemVerilog, UVM, and simulation tools; strong collaboration and AI/ML interest preferred.
Verilog/SystemVerilog, UVM, Synopsys VCS, Cadence Xcelium, Siemens Questa, Microsoft Excel
2w
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Design Verification Engineer (Silicon Engineering)
Palo Alto, California, United States
$135k-$210k/yr OnsiteFull Time
1+ YOEBachelor's in EE/CS/CompE,1+ years design verification experience, SystemVerilog/UVM, Python/MATLAB scripting, testbench and coverage development, RTL and pre/post-silicon validation experience.
SystemVerilog, UVM, Python, MATLAB
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