58 design verification engineer jobs at 28 companies in Sun City, CA
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Design Verification Engineer
Aliso Viejo or San Jose or Córdoba or Toronto
OnsiteFull Time
3+ YOEBachelors in EE/CE/CS,3+ years verification experience, SystemVerilog/UVM, coverage-driven verification, C/C++ and scripting (Python,Tcl,Perl),test planning and debug skills.
SystemVerilog, UVM, C, C++, Python, Tcl, Perl
3w
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Design Verification Engineer
Broomfield or San Diego or Fort Collins or San Jose or Irvine
$144k-$230k/yr OnsiteFull Time
10+ YOE12+ years verification experience for complex digital and mixed-signal circuits; proficiency with SystemVerilog/UVM/SVA, scripting, simulation tools, and RTL/gate-level debug; BS/MS in EE/CE.
SystemVerilog, UVM, SVA, Synopsys, Cadence, Mentor, Perl, Python, Tcl, DesignSync, git, Palladium, Veloce, Zebu, Xilinx, ICL, PDL, Tessent
2mo
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Design Verification Engineer - Viasat Government
Marlborough or Carlsbad
$133k-$210k/yr OnsiteFull Time
5+ YOEBachelor's in Electrical or Computer Engineering; 5+ years hardware verification with SystemVerilog/UVM; RTL verification; strong SystemVerilog/UVM; experience with industry EDA tools; US citizenship and active Secret clearance; willingness to travel up to 10%
SystemVerilog, UVM, Siemens Questa, Cadence, Synopsys, Mentor, Python, TCL
3mo
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Principal Design Verification Engineer (Silicon Engineering)
Sunnyvale or Austin or Irvine or Redmond
$210k-$310k/yr OnsiteFull Time
10+ YOEBachelor’s in electrical/computer engineering or computer science; 10+ years in design verification and test bench development.
UVM, OVM, VMM, Python, RTL
2w
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Staff Design Verification Test Engineer
Costa Mesa, California, United States
$191k-$253k/yr OnsiteFull Time
12+ YOEBachelor's degree in engineering, physics, or related field; 12+ years in test, verification, or product engineering; RF/microwave measurement, DVT, NPI, failure triage, and engineering leadership experience.
Lattice OS, spectrum analyzers, signal analyzers, VNAs, signal generators, power meters
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Design Verification Engineer - Viasat Government
Marlborough or Carlsbad
$133k-$210k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE or related,5+ years hardware verification experience with SystemVerilog/UVM,experience with industry EDA tools,US citizenship and active Secret clearance required,ability to travel up to 10%.
SystemVerilog, UVM, Siemens Questa, Cadence, Synopsys, Mentor, AMD/Xilinx Vivado, Altera Quartus, Microchip Libero, TCL, Perl, Python, Linux
3mo
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Sr. Satellite Design Verification Engineer, Amazon Leo
Irvine or Austin or Sunnyvale or Redmond or San Diego
OnsiteFull Time
7+ YOEBachelor's in Electrical/Communications Engineering; 3+ years UVM/SystemC/DPI-C; 7+ years verification in communications; preferred advanced degree; Matlab familiarity; DV/integration experience.
UVM, C, SystemC, DPI-C, Matlab
6d
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ASIC / FPGA Design Verification Engineer - (Associate or Experienced)
El Segundo or Huntington Beach
$99k-$162k/yr OnsiteFull Time
2+ YOEBachelor's degree and 2+ years of ASIC, FPGA, or SoC verification experience, or master's with related coursework. Requires digital verification fundamentals, SystemVerilog, U.S. citizenship, and ability to obtain Secret clearance.
SystemVerilog, UVM, UVC
6d
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ASIC / FPGA Design Verification Engineer - (Associate or Experienced)
El Segundo or Huntington Beach
$99k-$162k/yr OnsiteFull Time
2+ YOEBachelor's degree or equivalent in a related technical field, 2+ years of relevant verification experience or related master's coursework, digital verification fundamentals, SystemVerilog, U.S. citizenship, and ability to obtain a Secret clearance.
SystemVerilog, UVM
1w
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RFIC design engineer
Irvine, California, United States
OnsiteFull Time
Requires advanced understanding of RFIC design, simulation, layout, and verification; deep submicron process experience; industrial experience; and a Ph.D. or Master of Science in Electrical Engineering.
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Principal Analog Design Engineer
Irvine or San Jose or Vancouver or Ottawa
$150k-$250k/yr OnsiteFull Time
5+ YOEMaster’s or PhD in electrical engineering or a related field, 5+ years of experience, strong analog design fundamentals, and experience with Virtuoso, Spectre, ADE, and advanced CMOS verification flows.
Virtuoso, Spectre, ADE, EMX, Momentum, HFSS, CMOS, FinFET, PLL, VCOs, VGA, CTLE, DRV, LDOs
1d
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Sr. Mechanical Design Engineer
Santa Ana, California, United States
$120k-$150k/yr OnsiteFull Time
7+ YOEBachelor’s degree in mechanical engineering or related discipline; 7+ years’ regulated product design experience; 5+ years’ SolidWorks or 3D CAD experience; medical device, design control, verification, validation, FDA, and 510(k) experience.
SolidWorks, 3D CAD, FDA, ISO, IEC, Design History File (DHF), 510(k)
2mo
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Sr. Principal AMS Verification Engineer (Irvine, CA, US)
Irvine, California, United States
$143k-$286k/yr OnsiteFull Time
8+ YOERequires BS+15 yrs (MS+12 or PhD+8) experience; strong AMS design/verification background, Verilog-A and SystemVerilog RNM modeling, Cadence Virtuoso/ADS experience, Python scripting, leadership and communication skills.
Cadence Virtuoso, ADS, Verilog-A, SystemVerilog, SystemVerilog Real Number Modeling (RNM), Python
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Digital Design Engineer
Irvine, California, United States
$98k-$144k/yr OnsiteFull Time
1+ YOE1+ years experience designing and verifying high-performance communications/DSP ASICs; strong RTL (Verilog/System Verilog) and UNIX-based EDA tool skills; experience with verification, synthesis, lint, CDC, power analysis; MATLAB/C++ a plus.
Verilog, System Verilog, UNIX, EDA, MATLAB, C/C++
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RFIC - PLL Design Engineer
Irvine, California, United States
OnsiteFull Time
Design and validate RFIC phase-locked loops (PLLs) and radio transceivers for wireless SoCs; collaborate across RF/analog, systems, VLSI, verification, test, and firmware/software teams.
2mo
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Senior Principal Digital Design Engineer
Irvine, California, United States
$186k-$228k/yr OnsiteFull Time
6+ YOEExpert digital ASIC design experience, SystemVerilog/RTL implementation, block/system verification, synthesis/power/timing analysis, and technical leadership; BS in EE (or advanced) plus extensive experience.
SystemVerilog, Verilog, UVM, SystemC, PCIe, PCI-SIG, IEEE 802.3, SDC
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Staff FPGA Design Engineer
Irvine, California, United States
$150k-$190k/yr OnsiteFull Time
8+ YOEBachelor's in EE/CE, 8+ years FPGA RTL architecture/development/verification, strong SystemVerilog or VHDL skills, experience with Microship Polarfire/AMD Zynq/Versal/Ultrascale, verification methodologies, Git, Python/Tcl/Bash, C/C++ on Linux, and eligibility for DoD security clearance.
SystemVerilog, VHDL, Microship Polarfire, AMD Zynq US+, Versal, AMD Ultrascale, Vivado, Mentor Modelsim/Questasim, AXI, PCIe, DDR4, DDR5, JESD204B, JESD204C, 100Gb ethernet, SPI, I2C, UART, CAN FD, LVDS, Git, Python, Tcl, Bash, Linux, C/C++
2d
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Senior Staff Digital Design Engineer - Audio DSP Algorithm
Bengaluru or Irvine
OnsiteFull Time
10+ YOEAdvanced electronics engineering degree and 10+ years developing digital blocks or systems for high-performance mixed-signal ICs; expertise in DSP, RTL, Verilog/SystemVerilog, verification, and analog/mixed-signal blocks.
MATLAB Simulink, Verilog, SystemVerilog, Python, C, C++, Perl, ASIC, RTL, ADC, DAC
1mo
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Senior Design Quality Engineer - Medical Devices
Carlsbad or Chicago or Raleigh or Durham or Greensboro or Pittsboro
$100k-$140k/yr HybridFull Time
5+ YOEBachelor's degree,5+ years relevant experience,knowledge of FDA 21 CFR 820/ISO 13485/ISO 14971,cGMP,GxP; experience with electromechanical devices, audits, risk management, and verification/validation.
2mo
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Director of Verification & Validation
Huntington Beach, California, United States
$180k-$230k/yr OnsiteFull Time
8+ YOEBachelor's in Biomedical or Mechanical Engineering, 8+ years Class III medical device V&V, knowledge of FDA and IEC/ISO standards, design control expertise, strong technical writing, and experience leading V&V teams.
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