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508 verification engineer jobs at 106 companies in Texas

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Verification Engineer
San Jose or San Diego or Austin or Longmont
$124k-$213k/yr HybridFull Time
AMD
AMDNASDAQ: AMD: Designs and manufactures computer processors and graphics technology.
Experience in IP/ASIC/FPGA verification using UVM, Verilog/SystemVerilog, scripting (Python/Perl), and developing test plans and regression suites; bachelor’s or master’s in computer or electrical engineering.
UVM, Verilog, System Verilog, Python, Perl, PCIe, CXL, NVMe, Ethernet, HLS
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3mo
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ASIC Verification Engineer
Austin, Texas, United States
$116k-$190k/yr HybridFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs GPU-accelerated computing and artificial intelligence hardware.
2+ YOEBS/MS in Electrical or Computer Engineering; 2+ years ASIC/RTL verification; pre-silicon verification (UVM, SystemVerilog); RTL verification; Perl/Python; debugging; exposure to verification tools; strong communication.
UVM, SystemVerilog, Perl, Python, dc_shell, VCS, GDB, Debussy
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1mo
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Design Verification Engineer
Lakeway or Austin
OnsiteFull Time
Verilab
Verilab: Provides specialized functional verification services for ASIC and FPGA designs.
7+ YOEBSc/MSc in engineering or CS, 7+ years verification experience, expert SystemVerilog/UVM development, protocol verification (AXI, DDRx, PCIe, USBx), verification planning, and ability to travel; eligible to work in the US.
SystemVerilog, UVM, Specman/e, C, C++, Python, Perl
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1mo
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Sr Principal Verification Engineer
Austin, Texas, United States
$171k-$296k/yr OnsiteFull Time
GlobalFoundries
GlobalFoundriesNASDAQ: GFS: Manufacturer of semiconductors and provider of wafer fabrication services.
15+ YOEDesign verification of CPU cores; 15+ years exp; Bachelor's in Electronics/Electrical/Computer Engineering; SystemVerilog/UVM, scripting (Python/Perl/Shell); CPU/SoC verification experience.
SystemVerilog, UVM, Python, Perl, Shell, C, Assembly
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2mo
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Principal Verification Engineer
Austin or Santa Clara
OnsiteFull Time
SiFive
SiFive: Designs and licenses high-performance RISC-V processor intellectual property.
12+ YOE+12 years of experience; BS or MS in Computer Science, Electrical Engineering, or related field; experience with microarchitecture, CPU design, verification flow; strong analytical and troubleshooting skills; ability to collaborate across teams.
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3mo
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Formal Verification Engineer
Austin or Beaverton or Cupertino
OnsiteFull Time
Apple
AppleNASDAQ: AAPL: Designs and sells consumer electronics, software, and online services.
0+ YOEBachelor's degree in electrical or computer engineering with 0 years of experience; strong Verification knowledge preferred.
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2mo
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Design Verification Engineer (Data Fabric Verification Engineer)
Austin, Texas, United States
$45k-$121k/yr OnsiteFull Time
Wipro
WiproNYSE: WIT: Global technology services and consulting for digital transformation.
3+ YOE3-5 years VLSI/HVL verification experience; strong SystemVerilog and UVM skills; scripting with Perl, Ruby, or Make; familiarity with RTL, formal verification, and tools such as VCS, Cadence, and Mentor Graphics; bachelor's or master's in computer/electrical engineering preferred.
SystemVerilog, UVM, Perl, Ruby, Make, VCS, Cadence, Mentor Graphics
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Verification Engineer Senior
Austin, Texas, United States
$191k-$269k/yr HybridFull Time
Intel
IntelNasdaq: INTC: Designs and manufactures microprocessors and semiconductor components.
6+ YOEBachelor's in EE/CE/CS + 8+ yrs or Master's + 6+ yrs in ASIC/FPGA verification; SystemVerilog/UVM, OOP, coverage-driven verification, constrained-random testing, protocol experience (AXI, CHI, UART, SPI, I2C/I3C), strong debug skills.
SystemVerilog, UVM, Synopsys VCS, Cadence Xcelium
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3mo
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Design Verification Engineer
Austin or Chandler or Greensboro
HybridFull Time
Cirrus Logic
Cirrus LogicNASDAQ: CRUS: Designs mixed-signal integrated circuits for consumer electronics.
0+ YOEBachelor/Master/PhD in Electrical/Computer Engineering or related field; 2+ years with Bachelors; strong HDL/SystemVerilog/UVM; ASIC/silicon verification experience.
Verilog, VHDL, SystemVerilog, UVM
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ASIC Verification Engineer
Austin, Texas, United States
OnsiteFull Time
Retym
Retym: Developing coherent DSP silicon for AI data center infrastructure.
5+ YOE5+ years verification experience, 2+ full block/system verification cycles, deep VLSI verification knowledge, experience with SystemVerilog/UVM/eRM, familiarity with data-paths/protocols (Ethernet preferred), mentoring and cross-team collaboration.
SystemVerilog, UVM, eRM, RTL, Ethernet
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Senior Verification Engineer
Austin, Texas, United States
OnsiteFull Time
NXP Semiconductors
NXP SemiconductorsNASDAQ: NXPI: Designs and manufactures semiconductors for automotive and IoT applications.
5+ YOEBSEE+5yrs or MSEE+3yrs or PhD+1yr; expertise in Verilog/SystemVerilog, OVM/UVM, formal methods; knowledge of DDR, PCIe, AMBA; scripting in Python/Perl and UNIX/Linux; strong debugging and verification planning skills.
Verilog, SystemVerilog, VHDL, OVM/UVM, SystemVerilog assertions (SVA), DDR, PCIe, AMBA (CHI, ACE, AXI), AI/LLM, Python, Perl, UNIX/Linux
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2mo
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Sr/Staff Design Verification Engineer, HBM Verification Architecture
Richardson, Texas, United States
OnsiteFull Time
Micron Technology
Micron TechnologyNASDAQ: MU: Manufacturer of semiconductor memory and data storage products.
4+ YOEBachelor's in EE/CE, 4+ years verification engineering experience (digital/analog/mixed-signal), 2+ years in custom or RTL verification flows, strong debug and communication skills, EM/SoC verification experience preferred.
Verilog, FastSpice, RTL2GDS, GenAI
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ASIC Verification Engineer
Austin, Texas, United States
$116k-$190k/yr HybridFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs graphics processing units and artificial intelligence hardware.
2+ YOEBS/MS in Electrical/Computer Engineering or equivalent, 2+ years verification experience, SystemVerilog/UVM, Perl or Python scripting, experience with synthesis/simulation and debug tools, strong debugging and collaboration skills.
SystemVerilog, UVM, Perl, Python, dc_shell, VCS, Debussy, GDB
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1mo
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Design Engineer, Verification
Richardson, Texas, United States
$86k-$184k/yr OnsiteFull Time
GlobalFoundries
GlobalFoundriesNASDAQ: GFS: Semiconductor foundry providing chip design and fabrication services.
1+ YOEDegree in electrical/electronics/computer engineering, 1–5 years experience (depending on degree), knowledge of Verilog/SystemVerilog, UNIX, Assembly, C, Python/Perl, hardware/IP/SOC verification, and strong communication skills.
RISC-V, Verilog, SystemVerilog, UNIX, Assembly, C, Python, Perl
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Design Verification Engineer - APS
Dallas, Texas, United States
OnsiteFull Time
Texas Instruments
Texas InstrumentsNASDAQ: TXN: Designs and manufactures semiconductors and integrated circuits.
8+ YOEBachelor's degree in electrical engineering; 8+ years of experience; strong verification skills and Python, Verilog/SystemVerilog, UVM experience.
UVM, Verilog, SystemVerilog, Python
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Design Verification Engineer
Raleigh or Hillsboro or Austin or Mountain View or Redmond
$102k-$202k/yr HybridFull Time, Contract
Microsoft
MicrosoftNASDAQ: MSFT: Develops software, services, devices, and cloud computing solutions.
1+ YOEMaster's+1 or Bachelor's+2 years technical engineering experience (or equivalent); verification of silicon/IP using UVM/System Verilog/Formal; Python scripting; knowledge of CHI/AMBA/PCIe/CXL preferred; pass Microsoft Cloud Background Check and export-control screening.
UVM, Formal, System Verilog, Python
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1mo
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Principal Digital Verification Engineer
Plano, Texas, United States
OnsiteFull Time
Renesas Electronics
Renesas ElectronicsTokyo Stock Exchange: 6723: Designs and manufactures semiconductors for automotive and industrial systems.
8+ YOE8+ years in verification; MS in Electrical/Computer Engineering or equivalent; BS with 10+ years; UVM and SystemVerilog experience; DDR5 verification
UVM, SystemVerilog, Verilog, DDR5
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2w
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Mixed Signal Verification Engineer
Richardson, Texas, United States
OnsiteFull Time
Qorvo
QorvoNASDAQ: QRVO: Designs and manufactures radio frequency and power semiconductor solutions.
0+ YOEMaster's in electrical engineering (or related), 0–2 years AMS design/verification experience, proficiency with mixed-signal verification methodology, and strong problem-solving and communication skills.
System Verilog, VerilogAMS, UVM, TLDV, RNM
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ASIC Engineer, Design Verification
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
Meta
MetaNASDAQ: META: Develops social networking platforms and virtual reality technologies.
6+ YOEBachelor's in CS/CE or equivalent; 6+ years SystemVerilog/UVM or C/C++ verification and IP/SoC level verification experience; EDA tools and scripting (Python, TCL, Perl, Shell).
SystemVerilog, UVM, C, C++, Python, TCL, Perl, Shell, Mercurial, Hg, Git, SVN, SV Assertions, Formal, Emulation, PCIe, RoCE, DDR, HBM, Ethernet
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Senior Design Verification Engineer
Dallas, Texas, United States
OnsiteFull Time
Analog Devices
Analog DevicesNASDAQ: ADI: Designs and manufactures semiconductors for signal processing and power management.
4+ YOEExpert SystemVerilog and UVM skills, testbench development, verification planning, scripting (Python, Perl, TCL), mixed-signal verification, debugging, and technical leadership; Bachelor’s required, 4+ years relevant experience.
SystemVerilog, UVM, Python, Perl, TCL
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